Systems and methods for minimizing harmonic interference
View Patent ↗Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency.
1. A clock generator, comprising:
a high frequency clock/oscillator;
a counter coupled to the clock/oscillator, wherein the counter is coupled to receive a first count value and a second count value to set an asymmetrical duty cycle; and
a controller coupled to receive an output of the counter to generate a low frequency clock with the asymmetrical duty cycle.
2. The clock generator of claim 1 , wherein the clock/oscillator is configured to generate an output at a high frequency relative to the low frequency clock.
3. The clock generator of claim 1 , wherein the counter is a down counter.
4. The clock generator of claim 1 , wherein the counter is a modulo counter.
5. The clock generator of claim 1 , wherein the controller to change the position of a falling edge of a symmetrical clock relative to the position of a rising edge of the symmetrical clock to obtain the asymmetrical duty cycle.
6. The clock generator of claim 1 , wherein the controller to minimize the nth-order harmonic and change the magnitude of another harmonic.
7. An apparatus comprising:
an oscillator to generate a first clock signal with a first duty cycle at a first frequency;
a counter coupled to the oscillator; and
a controller to generate a second clock signal at the first frequency with a second duty cycle formed by a first transition and a second transition, the second transition initiated when a value of the counter is at a predetermined value.
8. The apparatus of claim 7 , wherein the oscillator is at an intermediate frequency.
9. The apparatus of claim 7 , further comprising a digital portion.
10. The apparatus of claim 9 , wherein the oscillator and the digital portion are on a single substrate.
11. The apparatus of claim 10 , wherein the second clock signal to be provided to the digital portion.
12. The apparatus of claim 7 , wherein the counter is coupled to receive a first count value and a second count value to set the second duty cycle.