Method and apparatus for adaptive cache frame locking and unlocking
A method and apparatus are disclosed for locking the most recently accessed frames in a cache memory. The most recently accessed frames in a cache memory are likely to be accessed by a task again in the near future. The most recently used frames may be locked at the beginning of a task switch or interrupt to improve the performance of the cache. The list of most recently used frames is updated as a task executes and may be embodied, for example, as a list of frames addresses or a flag associated with each frame. The list of most recently used frames may be separately maintained for each task if multiple tasks may interrupt each other. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks frames that may cause a significant performance degradation for a task. The adaptive frame unlocking mechanism monitors a number of times a task experiences a frame miss and unlocks a given frame if the number of frame misses exceeds a predefined threshold.
1. A cache memory, comprising:
a plurality of cache frames for storing information from main memory; and
an adaptive frame locking mechanism for locking a number of most recently used frames associated with a task, wherein said adaptive frame locking mechanism includes three latches (a 1 , b 1 , and lock) for each frame of said cache and wherein said latch a 1 is set when an associated frame is accessed and the value in latch a 1 of a frame is transferred to latch b 1 after n accesses and latch a 1 is reset after the value in latch a 1 of the frame is transferred to latch b 1 , and wherein a frame is locked if one or more of latch a 1 and latch b 1 are locked when a lock signal is asserted.
2. The cache memory of claim 1 , further comprising a memory for recording an identifier of the n most recently used frames.
3. The cache memory of claim 2 , wherein said identifier is a frame address.
4. The cache memory of claim 2 , wherein said identifier is a flag associated with said most recently used frames.
5. The cache memory of claim 2 , wherein said identifier of the n most recently used frames is maintained for each of a plurality of tasks.
6. The cache memory of claim 1 , wherein said adaptive frame locking mechanism does not lock all the frames in a set concurrently.
7. The cache memory of claim 1 , wherein said number of said most recently used frames identities the most recently accessed 3n/2 frames on average.
8. The cache memory of claim 1 , wherein said adaptive frame locking mechanism sets a lock latch of a given frame, locking the frame, if either latch a 1 or latch b 1 is set when the lock signal is asserted.
9. The cache memory of claim 1 , further comprising an adaptive frame unlocking mechanism that automatically unlocks frames that cause a performance degradation for a task.
10. The cache memory of claim 9 , wherein said adaptive frame unlocking mechanism includes a counter for monitoring a number of times a task experiences a frame miss.
11. The cache memory of claim 1 , wherein said cache is a two way set associative cache and said most recently used frames are identified by taking an inverse of a least recently used identifier.
12. The cache memory of claim 1 , wherein said locking is performed if a first task is interrupted by a second task.
13. An integrated circuit, comprising:
a cache memory having a plurality of cache frames for storing information from main memory; and
an adaptive frame locking mechanism for locking a number of most recently used frames associated with a task, wherein said adaptive frame locking mechanism includes three latches (a 1 , b 1 , and lock) for each frame of said cache and wherein said latch a 1 is set when an associated frame is accessed and the value in latch a 1 of a frame is transferred to latch b 1 after n accesses and latch a 1 is reset after the value in latch a 1 of the frame is transferred to latch b 1 , and wherein a frame is locked if one or more of latch a 1 and latch b 1 are locked when a lock signal is asserted.
14. The integrated circuit of claim 13 , further comprising a memory for recording an identifier of the n most recently used frames.
15. The integrated circuit of claim 13 , further comprising an adaptive frame unlocking mechanism that automatically unlocks frames that cause a performance degradation for a task.
16. The integrated circuit of claim 13 , wherein said locking is performed if a first task is interrupted by a second task.
17. A cache memory device comprising:
a memory element for storing information from main memory in frames of said cache memory device;
a monitor for monitoring a number of most recently used frames; and
an adaptive frame locking mechanism for locking said number of said most recently used frames if a task is interrupted by another task, wherein said adaptive frame locking mechanism includes three latches (a 1 , b 1 , and lock) for each frame of said cache and wherein said latch a 1 is set when an associated frame is accessed and the value in latch a 1 of a frame is transferred to latch b 1 after n accesses and latch a 1 is reset after the value in latch a 1 of the frame is transferred to latch b 1 , and wherein a frame is locked if one or more of latch a 1 and latch b 1 are locked when a lock signal is asserted.
18. The cache memory device of claim 17 , wherein said adaptive frame locking mechanism does not lock all the frames in a set concurrently.
19. The cache memory device of claim 17 , wherein said adaptive frame locking mechanism automatically unlocks frames that cause a significant performance degradation for a task.
20. The cache memory device of claim 17 , wherein said cache is a two way set associative cache and said most recently used frames are identified by taking an inverse of a least recently used identifier.