Granted Patent
Utility
US 6,452,861
· Confirmation No. 7589
SEMICONDUCTOR MEMORY DEVICE ALLOWING SIMULTANEOUS INPUTTING OF N DATA SIGNALS
Inventor:
Masakazu Hirose
Patented Case
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2011-01-06 | PET.AUTO |
ePetition Request Form | 3 | View | |
| 2011-01-06 | WFEE |
Fee Worksheet (SB06) | 2 | View | |
| 2011-01-06 | PET.DEC.AUTO |
ePetition Grant Letter | 1 | View | |
| 2011-01-06 | N417 |
Electronic Filing System Acknowledgment Receipt | 2 | View | |
| 2001-10-19 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-10-19 | SPEC |
Specification | 23 | View | |
| 2001-10-19 | CLM |
Claims | 3 | View | |
| 2001-10-19 | ABST |
Abstract | 1 | View | |
| 2001-10-19 | DRW |
Drawings-only black and white line drawings | 14 | View | |
| 2001-10-19 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Masakazu Hirose
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/230.06
G11C11/4063
G11C29/26
G11C7/1006
G11C7/18
G11C8/12
Prosecution
- Examiner
- DINH, SON T
- Art Unit
- 2824
- Docket No.
- 57454-226
- Confirmation No.
- 7589
Foreign Priority
2001-125644 (P)
·
2001-04-24
·
JAPAN
Patent Term Adjustment
0days
No related applications found.
from
DRAM MEMTECH LLC
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-05
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-01-31
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2010-11-13
from
HIROSE, MASAKAZU
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-10-19
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Quick Facts
- Patent No.
- US 6,452,861
- App. No.
- 09/981,811
- Filed
- 2001-10-19
- Granted
- 2002-09-17
- Examiner
- DINH, SON T
- Art Unit
- 2824
- PTA
- 0 days
External Links