Granted Patent
Utility
US 6,452,862
· Confirmation No. 7502
SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL WORD LINE STRUCTURE
Inventor:
Hiroshi Tomotani
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-10-19 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-10-19 | SPEC |
Specification | 48 | View | |
| 2001-10-19 | CLM |
Claims | 4 | View | |
| 2001-10-19 | ABST |
Abstract | 1 | View | |
| 2001-10-19 | DRW |
Drawings-only black and white line drawings | 13 | View | |
| 2001-10-19 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Hiroshi Tomotani
Osaka, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/230.06
Prosecution
- Examiner
- PHAN, TRONG Q
- Art Unit
- 2818
- Docket No.
- 60188-102
- Confirmation No.
- 7502
Foreign Priority
2000-322131
·
2000-10-23
·
JAPAN
Publication
- Pub. No.
- US20020048210A1
- Pub. Date
- 2002-04-25
Patent Term Adjustment
-93days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2020-05-27
CHANGE OF NAME
Recorded 2020-03-18
from
TOMOTANI, HIROSHI
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-10-19
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Quick Facts
- Patent No.
- US 6,452,862
- App. No.
- 09/981,981
- Filed
- 2001-10-19
- Granted
- 2002-09-17
- Pub. No.
- US20020048210A1
- Examiner
- PHAN, TRONG Q
- Art Unit
- 2818
- PTA
- -93 days
External Links