Semiconductor device, a method of manufacturing the same and storage media
View Patent ↗Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
1. A semiconductor device comprising a plurality of signal terminals of a circuit block,
wherein the signal terminals are arranged within a frame of the circuit block and along a second direction that intersects a first direction along which a plurality of wirings extend, the wirings are wirings of an upper layer and outside the circuit block, and the wirings are connected to the signal terminals via a plurality of through holes,
wherein each of the signal terminals extends in the second direction so that a dimension thereof in the second direction passes through at least two of the plurality of wirings.
2. The semiconductor device according to claim 1 , wherein a plurality of the circuit blocks are arranged along the first direction of the wiring outside the circuit blocks, and the signal terminals of each of the circuit blocks and the wiring outside the circuit blocks are electrically connected to each other.
3. The semiconductor device according to claim 2 , wherein a wiring area is provided between a group of circuit blocks among the circuit blocks.
4. The semiconductor device according to claim 1 , wherein the signal terminals are constituted of a top wiring layer in the circuit block.
5. The semiconductor device according to claim 1 , wherein the circuit block is a memory circuit, and one of the signal terminals is formed on an input/output circuit area of the memory circuit.
6. The semiconductor device according to claim 5 , wherein the memory circuit constitutes a Random Access Memory.
7. A semiconductor device, comprising:
a plurality of circuit blocks arranged along a first direction; and
wirings that extend in the first direction and electrically connects between the plurality of circuit blocks,
wherein a plurality of signal terminals are arranged in a frame of each of the plurality of circuit blocks and along a second direction that intersects the first direction;
wherein each of the plurality of signal terminals extends in the second direction so that a dimension thereof in the second direction passes through at least two of the wirings; and
wherein the wirings are arranged on an upper layer outside the circuit block and are electrically connected to the plurality of signal terminals via a plurality of through holes.
8. The semiconductor device according to claim 7 , wherein each of the plurality of signal terminals is constituted of a top wiring layer in the circuit block.
9. The semiconductor device according to claim 7 , wherein one of the circuit blocks is a memory circuit, one of the wirings constructs a wiring for an address signal, and said one of the wirings is connected in common to said one of the circuit blocks.
10. The semiconductor device according to claim 7 , wherein one of the circuit blocks is a memory circuit, one of the wirings is wiring for data input, and t said one of the wirings is connected in common to said one of the circuit blocks.
11. The semiconductor device according to claim 7 , wherein one of the circuit blocks is connected to a wiring for a different clock signal.
12. The semiconductor device according to claim 7 ,
wherein one of the circuit blocks is a memory circuit, and
wherein one of the signal terminals is formed on an input/output circuit area of the memory circuit.
13. The semiconductor device according to claim 12 ,
wherein one of the wirings is a wiring for an address signal or a wiring for data.
14. The semiconductor device according to claim 9 , wherein the memory circuit constitutes a Random Access Memory.
15. The semiconductor device according to claim 10 , wherein the memory circuit constitutes a Random Access Memory.
16. A semiconductor device, comprising:
a plurality of memory circuits arranged along a first direction; and
a plurality of first wirings extending in the first direction and being electrically connected to the plurality of memory circuits,
wherein a plurality of signal terminals are arranged in a frame of each of the plurality of memory circuits and along a second direction that intersects the first direction;
wherein the plurality of first wirings are formed on an upper layer outside the circuit block and, and extend over the signal terminals;
wherein each of the signal terminals extends in the second direction so that a dimension thereof in the second direction passes through at least two of the first wirings; and
wherein the plurality of first wirings are electrically connected to the signal terminals via a plurality of through holes.
17. The semiconductor device according to claim 16 , comprising:
a second wiring formed on the upper layer as the first wiring,
wherein the second wiring is electrically connected to each of the signal terminals of the plurality of memory circuits positioned on an identical wiring channel.
18. The semiconductor device according to claim 16 , wherein one of the first wirings is a wiring for an address signal.
19. The semiconductor device according to claim 16 , wherein one of the first wirings is a wiring for data.
20. The semiconductor device according to claim 16 , wherein one of the first wirings is a wring for a clock signal.
21. The semiconductor device according to claim 17 ,
wherein one of the first wirings is for an address signal and another one of the first wirings is for data; and
wherein the second wiring is the for an address signal or for data.
22. The semiconductor device according to claim 21 , wherein one of the memory circuits constitutes a Random Access Memory.