Semiconductor device for data communication control and radio communication apparatus
View Patent ↗The required RAM capacity is reduced by dividing an interleaving RAM in a baseband modulator into a plurality of areas and having the read side and the write side use some common areas on a time-sharing basis.
1. A semiconductor device for improving data interleaving/de-interleaving efficiency, comprising:
a memory; and
a control circuit for writing a first set of data into a first area of the memory according to a predetermined interleaving/de-interleaving manner, for reading out a portion of the firstly written data from the first area of the memory, and for writing a portion of a second set of data to be interleaved/de-interleaved right after said first set of data into a portion of the first area of the memory where the read-out portion of said first set of data was written.
2. A semiconductor device for improving data interleaving/de-interleaving efficiency, comprising:
a memory;
a writing circuit for writing a first set of data into a first area of the memory according to a predetermined interleaving/de-interleaving manner;
a reading circuit for reading out a portion of the firstly written data from the first area of the memory; and
a writing circuit for writing a portion of a second set of data to be interleaved/de-interleaved right after said first set of data into a portion of the first area of the memory where the read-out portion of said first set of data was written.
3. A semiconductor device for improving data interleaving/de-interleaving efficiency, comprising:
a first memory area;
a second memory area;
a third memory area; and
a control circuit for writing a first set of data into the first memory area and the second memory area according to a predetermined interleaving/de-interleaving manner, for reading out a first portion of the first set of data from the first memory area and a second portion of the first set of data from the second memory area, for writing a second set of data, which will be interleaved/de-interleaved right after said first set of data, into the first memory area after the first portion of said first set of data has been read out from the first memory area.
4. A semiconductor device for improving data interleaving/de-interleaving efficiency, comprising:
a first memory area;
a second memory area;
a third memory area;
a writing circuit for writing a first set of data into the first memory area and the second memory area according to a predetermined interleaving/de-interleaving manner;
a reading circuit for reading out a first portion of the first set of data from the first memory area and for reading out a second portion of the first set of data from the second memory area; and
a writing circuit for writing a second set of data, which will be interleaved/de-interleaved right after said first set of data, into the first memory area after the first portion of said first set of data has been read out from the first memory area.
5. The semiconductor device according to claim 3 , wherein the second set of data is written into the third memory area before the second portion of said first set of data has been read out from the second memory area.
6. The semiconductor device according to claim 3 , wherein said first memory area is greater than said second memory area, and said first memory area is greater than said third memory area.
7. The semiconductor device according to claim 3 , wherein said first memory area, said second memory area and said third memory area are of the same size.
8. The semiconductor device according to claim 3 , wherein the first memory area is selected via a frame timing signal or an address signal.
9. The semiconductor device according to claim 4 , wherein the second set of data is written into the third memory area before the second portion of said first set of data has been read out from the second memory area.
10. The semiconductor device according to claim 4 , wherein said first memory area is greater than said second memory area, and said first memory area is greater than said third memory area.
11. The semiconductor device according to claim 4 , wherein said first memory area, said second memory area and said third memory area are of the same size.
12. The semiconductor device according to claim 4 , wherein the first memory area is selected via a frame timing signal or an address signal.
13. A communication apparatus comprises an antenna for transmitting and receiving data, and a baseband modulator having at least one semiconductor device for improving data interleaving/de-interleaving efficiency which includes:
a first memory area;
a second memory area;
a third memory area; and
a control circuit for writing a first set of data into the first memory area and the second memory area according to a predetermined interleaving/de-interleaving manner, for reading out a first portion of the first set of data from the first memory area and a second portion of the first set of data from the second memory area, for writing a second set of data, which will be interleaved/de-interleaved right after said first set of data, into the first memory area after the first portion of said first set of data has been read out from the first memory area.
14. A communication apparatus comprises an antenna for transmitting and receiving data, and a baseband modulator which includes:
a first memory area;
a second memory area;
a third memory area;
a writing circuit for writing a first set of data into the first memory area and the second memory area according to a predetermined interleaving/de-interleaving manner;
a reading circuit for reading out a first portion of the first set of data from the first memory area and for reading out a second portion of the first set of data from the second memory area; and
a writing circuit for writing a second set of data, which will be interleaved/de-interleaved right after said first set of data, into the first memory area after the first portion of said first set of data has been read out from the first memory area.
15. The communication apparatus according to claim 13 , wherein the second set of data is written into the third memory area before the second portion of said first set of data has been read out from the second memory area.
16. The communication apparatus according to claim 13 , wherein said first memory area is greater than said second memory area, and said first memory area is greater than said third memory area.
17. The communication apparatus according to claim 13 , wherein said first memory area, said second memory area and said third memory area are of the same size.
18. The communication apparatus according to claim 13 , wherein the first memory area is selected via a frame timing signal or an address signal.
19. The communication apparatus according to claim 14 , wherein the second set of data is written into the third memory area before the second portion of said first set of data has been read out from the second memory area.
20. The communication apparatus according to claim 14 , wherein said first memory area is greater than said second memory area, and said first memory area is greater than said third memory area.
21. The communication apparatus according to claim 14 , wherein said first memory area, said second memory area and said third memory area are of the same size.
22. The communication apparatus according to claim 14 , wherein the first memory area is selected via a frame timing signal or an address signal.
23. A communication apparatus comprises an antenna for transmitting and receiving data, and a baseband modulator which includes:
an interleaving circuit for interleaving to-be-transmitted data, said interleaving circuit further comprises:
a writing circuit for writing a first set of to-be-transmitted data into a first area of a storage medium according to a predetermined interleaving manner;
a reading circuit for reading out a portion of the firstly written to-be-transmitted data from the first area of the storage medium; and
a writing circuit for writing a portion of a second set of to-be-transmitted data which will be interleaved right after said first set of to-be-transmitted data into a portion of the first area of the storage medium where the read-out portion of said first set of to-be-transmitted data was written,
a transmitter for transmitting the interleaved data between two different locations;
a receiver for receiving data transmitted between the two different locations; and
a de-interleaving circuit for de-interleaving the received data, the de-interleaving circuit further comprises:
a writing circuit for writing a first set of transmitted data into a second area of the storage medium according to a predetermined interleaving manner;
a reading circuit for reading out a portion of the firstly written transmitted data from the second area of the storage medium; and
a writing circuit for writing a portion of a second set of transmitted data which will be de-interleaved right after said first set of transmitted data into a portion of the second area of the storage medium where the read-out portion of said first set of transmitted data was written.
24. A communication apparatus comprises an antenna for transmitting and receiving data, and a baseband modulator which includes:
an interleaving circuit for interleaving to-be-transmitted data, said interleaving circuit further comprises:
a first memory area;
a second memory area;
a third memory area;
a writing circuit for writing a first set of to-be-transmitted data into the first memory area and the second memory area according to a predetermined interleaving manner;
a reading circuit for reading out a first portion of the first set of to-be-transmitted data from the first memory area and for reading out a second portion of the first set of to-be-transmitted data from the second memory area; and
a writing circuit for writing a second set of to-be-transmitted data, which will be interleaved right after said first set of to-be-transmitted data, into the first memory area after the first portion of said first set of to-be-transmitted data has been read out from the first memory area,
a transmitter for transmitting the interleaved data between two different locations;
a receiver for receiving data transmitted between the two different locations; and
a de-interleaving circuit for de-interleaving the received data, the de-interleaving circuit further comprises:
a fourth memory area;
a fifth memory area;
a sixth memory area;
a writing circuit for writing a first set of transmitted data into the fourth memory area and the fifth memory area according to a predetermined de-interleaving manner;
a reading circuit for reading out a third portion of the first set of transmitted data from the fourth memory area and for reading out a fourth portion of the first set of to-be-transmitted data from the second memory area; and
a writing circuit for writing a second set of transmitted data, which will be de-interleaved right after said first set of transmitted data, into the fourth memory area after the third portion of said first set of transmitted data has been read out from the fourth memory area.
25. The communication apparatus according to claim 24 , wherein the second set of to-be-transmitted data is written into the third memory area before the second portion of said first set of data has been read out from the second memory area.
26. The communication apparatus according to claim 24 , wherein said first memory area is greater than said second memory area, and said first memory area is greater than said third memory area.
27. The communication apparatus according to claim 24 , wherein said first memory area, said second memory area and said third memory area are of the same size.
28. The communication apparatus according to claim 24 , wherein the first memory area is selected via a frame timing signal or an address signal.
29. The communication apparatus according to claim 24 , wherein the second set of transmitted data is written into the sixth memory area before the fourth portion of said first set of data has been read out from the fifth memory area.
30. The communication apparatus according to claim 24 , wherein said fourth memory area is greater than said fifth memory area, and said fourth area is greater than said sixth memory area.
31. The communication apparatus according to claim 24 , wherein said fourth memory area, said fifth memory area and said sixth memory area are of the same size.
32. The communication apparatus according to claim 24 , wherein the fourth memory area is selected via a frame timing signal or an address signal.
33. The communication apparatus according to claim 24 , wherein:
the operating frequency of said baseband modulator is higher than the transmission rate of data transmitted from said antenna.
34. A method for improving data interleaving/de-interleaving efficiency, comprising:
writing a first set of data into a first area of a storage medium according to a predetermined interleaving/de-interleaving manner;
reading out a portion of the firstly written data from the first area of the storage medium; and
writing a portion of a second set of data to be interleaved-interleaved right after said first set of data into a portion of the first area of the storage medium where the read-out portion of said first set of data was written.
35. A method for improving interleaving efficiency of communication data comprises interleaving to-be-transmitted data, and transmitting the interleaved data between two different locations, said interleaving step further comprises:
writing a first set of to-be-transmitted data into a first area of a storage medium according to a predetermined interleaving manner;
reading out a portion of the firstly written to-be-transmitted data from the first area of the storage medium; and
writing a portion of a second set of to-be-transmitted data which will be interleaved right after said first set of to-be-transmitted data into a portion of the first area of the storage medium where the read-out portion of said first set of to-be-transmitted data was written.
36. A method for improving de-interleaving efficiency of communication data comprises receiving data transmitted between two different locations, and de-interleaving the received data, the de-interleaving step further comprises:
writing a first set of transmitted data into a first area of a storage medium according to a predetermined de-interleaving manner;
reading out a portion of the firstly written transmitted data from the first area of the storage medium; and
writing a portion of a second set of transmitted data which will be de-interleaved right after said first set of transmitted data into a portion of the first area of the storage medium where the read-out portion of said first set of transmitted data was written.
37. A computer program product for improving data interleaving/de-interleaving efficiency, comprising:
a module for writing a first set of data into a first area of a storage medium according to a predetermined interleaving/de-interleaving manner;
a module for reading out a portion of the firstly written data from the first area of the storage medium; and
a module for writing a portion of a second set of data to be interleaved/de-interleaved right after said first set of data into a portion of the first area of the storage medium where the read-out portion of said first set of data was written.
38. An apparatus for improving data interleaving/de-interleaving efficiency, comprising:
means for writing a first set of data into a first area of a storage medium according to a predetermined interleaving/de-interleaving manner;
means for reading out a portion of the firstly written data from the first area of the storage medium; and
means for writing a portion of a second set of data to be interleaved/de-interleaved right after said first set of data into a portion of the first area of the storage medium where the read-out portion of said first set of data was written.