Signal processing circuit
View Patent ↗In a data demodulating method, predetermined input data is demodulated based upon a response characteristic of the partial response class 4; the demodulated input data is discrete-filtered to thereby produce filtering data; and the filtering data is maximum likelihood-decoded to thereby produce asymmetrical response data. Further, a magnetic recording/reproducing apparatus is arranged by using this data demodulating method.
1. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into an asymmetrical waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein said coefficients (c 0 , c 1 . . . c n ) are integer numbers.
2. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into a waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein the output waveform of said discrete filter is (1−D 2 ) (c 0 +c 1 D+c 2 D 2 ), the coefficients (c 0 , c 1 , c 2 ) are (3, 2, 1) respectively.
3. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into a waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein the output waveform of said discrete filter is (1−D) (c 0 +c 1 D), and the coefficients (c 0 , c 1 , c 2 ) are (5, 4, 2) respectively.
4. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into a waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein the output waveform of said discrete filter is (1−D 2 ) (c 0 +c 1 D+c 2 D 2 ), and the coefficients (c 0 , c 1 , c 2 ) are (2, 2, 1) respectively.
5. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into a waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein the output waveform of said discrete filter is (1−D 2 ) (c 0 +c 1 D 2 +c 3 D 3 ), and the coefficients (c 0 , c 1 , c 2 , C 3 ) are (2, 5, 3, 2) respectively.
6. A signal processing circuit comprising:
an equalizer for equalizing an input signal based on partial response characteristics having (1−D 2 );
a discrete filter for converting the output from said equalizer into a waveform of (1−D 2 ) (c 0 +c 1 D+ . . . +c n D n ); and
a maximum-likelihood-demodulator for demodulating data output from said discrete filter,
wherein the output waveform of said discrete filter is (1−D 2 ) (c 0 ,+c 1 D+c 2 D 2 +c 3 D 3 ), and the coefficients (c 0 , c 1 , c 2 , c 3 ) are (2, 4, 2, 1) respectively.
7. A signal processing circuit comprising:
a discrete filter for converting an input signal into an asymmetrical response having a waveform of (1−D 2 )(c 0 +c 1 D+ . . . c n D n ) and
a maximum-likelihood-demodulator for demodulating output from said discrete filter based on said asymmetrical response, wherein said coefficients (c 0 , c 1 , . . . c n ) are integer numbers and (1−D 2 ) is the partial response characteristic of said input signal.
8. A signal processing circuit according to claim 7 , wherein said asymmetrical response is selected so that data demodulated by said maximum-likelihood-demodulator contains a specific error.
9. A signal processing circuit according to claim 7 , further comprising:
a register for setting coefficients of said asymmetrical response.
10. A signal processing circuit according to claim 7 , wherein the output from said maximum-likelihood-demodulator is directly outputted externally.
11. A signal processing circuit comprising:
an equalizer for equalizing an input signal into a symmetrical response;
a discrete filter for converting the output from said equalizer into an asymmetrical response having a waveform of (1−D 2 )(c 0 +c 1 D+ . . . c n D n ) and
a maximum-likelihood-demodulator for demodulating output from said discrete filter based on said asymmetrical response, wherein said coefficients (c 0 , c 1 , . . . c n ) are integer numbers and (1−D 2 ) is the partial response characteristic of said input signal.
12. A signal processing circuit according to claim 11 , wherein said discrete filter converts so that a data response outputted from said equalizer satisfies a minimum phase transitional condition.
13. A signal processing circuit according to claim 11 , further comprising:
an error corrector for correcting at least one bit error among demodulated data output from said maximum-likelihood-demodulator.
14. A signal processing circuit according to claim 11 , further comprising:
an error corrector for correcting at least continuous three bits error among demodulated data output from said maximum-likelihood-demodulator.