IP Library Granted Patent US 6,889,235
Granted Patent B2
US 6,889,235 · App. 09/991,098 · Granted May 3, 2005

Method and apparatus for quantifying the number of identical consecutive digits within a string

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Quick Facts
Patent No.
US 6,889,235
App. No.
09/991,098
Granted
May 3, 2005
Kind
B2
Abstract

One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

Claims (46)

1. A method for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits, comprising:

converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits;

wherein converting the string of digits into the thermometer code involves passing the string of digits through ┌log m n┐ layers of m-input AND gates, wherein for the case where m=2 a first layer of AND gates produces thermometer codes for sub-strings of length two, and wherein each consecutive layer produces thermometer codes for sub-strings of length k+1 to 2k by ANDing together thermometer codes for sub-strings of length 1 to k from preceding layers;

converting the thermometer code into a one-hot code in which only one bit has a logical one value; and

converting the one-hot code into a logarithmic code representing the number of identical consecutive digits.

2. The method of claim 1 ,

wherein converting the thermometer code into the one-hot code involves passing the thermometer code through a single layer of two-input comparator gates;

wherein a given comparator gate produces a logical one value when a first input of the comparator gate receives a logical one value and a second input receives a logical zero value; and

wherein a comparator gate is coupled between each consecutive pair of thermometer code bits, so that only one comparator gate, covering a boundary between consecutive logical ones and consecutive logical zeros, produces a logical one value.

3. The method of claim 1 , wherein converting the one-hot code into the logarithmic code involves passing the one-hot code through ┌log 2 n┐−1 layers of OR gates, wherein a given bit in the logarithmic code is produced by ORing together bits of the one-hot code that cause the given bit in the logarithmic code to be asserted.

4. The method of claim 1 , wherein the string of n digits is a string of n binary digits.

5. The method of claim 1 , wherein the fixed position in the string of n digits is the beginning of the string, so that the number of leading identical consecutive digits is quantified.

6. The method of claim 5 , wherein the number of leading zero values is quantified.

7. The method of claim 6 , further comprising using the logarithmic code to normalize a result of a floating-point arithmetic operation.

8. The method of claim 1 , further comprising using the logarithmic code to encode or decode a stream of data, wherein the logarithmic code represents a run-length of identical consecutive digits within the stream of data.

9. The method of claim 1 , wherein each digit in the string of n digits includes one or more binary digits.

10. An apparatus that quantifies a number of identical consecutive digits starting from a fixed position within a string of n digits, comprising:

a thermometer code circuit that converts the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits;

wherein the thermometer code circuit includes ┌log m n┐ layers of m-input AND gates, wherein for the case where m=2•a first layer of AND gates produces thermometer codes for sub-strings of length two, and wherein each consecutive layer produces thermometer codes for sub-strings of length k+1 to 2k by ANDing together thermometer codes for sub-strings of length 1 to k from preceding layers;

a one-hot code circuit that converts the thermometer code into a one-hot code in which only one bit has a logical one value; and

a logarithmic code circuit that converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

11. The apparatus of claim 10 ,

wherein the one-hot-code circuit includes a single layer of two-input comparator gates;

wherein a given comparator gate produces a logical one value when a first input of the comparator gate receives a logical one value and a second input receives a logical zero value; and

wherein a comparator gate is coupled between each consecutive pair of thermometer code bits, so that only one comparator gate, covering a boundary between consecutive logical ones and consecutive logical zeros, produces a logical one value.

12. The apparatus of claim 10 , wherein the logarithmic code circuit includes ┌log 2 n┐−1 layers of OR gates, wherein a given bit in the logarithmic code is produced by ORing together bits of the one-hot code that cause the given bit in the logarithmic code to be asserted.

13. The apparatus of claim 10 , wherein the string of n digits is a string of n binary digits.

14. The apparatus of claim 10 , wherein the fixed position in the string of n digits is the beginning of the string, so that the number of leading identical consecutive digits is quantified.

15. The apparatus of claim 14 , wherein the apparatus quantifies the number of leading zero values.

16. The apparatus of claim 15 , further comprising a floating-point arithmetic unit that is configured to use the logarithmic code to normalize a result of a floating-point arithmetic operation.

17. The apparatus of claim 10 , farther comprising an encoder that is configured to use the logarithmic code to encode or decode a stream of data, wherein the logarithmic code represents a run-length of identical consecutive digits within the stream of data.

18. The apparatus of claim 10 , wherein each digit in the string of n digits includes one or more binary digits.

19. A computer system including a circuit that quantifies a number of identical consecutive digits, comprising:

a processor;

a memory;

a quantifying circuit that quantifies the number of identical consecutive digits starting from a fixed position within a string of n digits, wherein the quantifying circuit includes;

a thermometer code circuit that converts the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits,

wherein the thermometer code circuit includes ┌log m n┐ layers of m-input AND gates, wherein for the case when m=2, a first layer of AND gates produces thermometer codes for sub-strings of length two, and wherein each consecutive layer produces thermometer codes for sub-strings of length k+1 to 2k by ANDing together thermometer codes for sub-strings of length 1 to k from preceding layers,

a one-hot code circuit that converts the thermometer code into a one-hot code in which only one bit has a logical one value; and

a logarithmic code circuit that converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

20. The computer system of claim 19 , further comprising:

a floating-point arithmetic unit of within the processor;

wherein the quantifying circuit is located within the floating-point arithmetic unit and is configured to normalize results of floating-point operations.

21. The computer system of claim 19 ,

wherein the computer system includes an encoding circuit for encoding or decoding streams of data; and

wherein the quantifying circuit is located within the encoding circuit and is configured to quantify run-lengths of identical consecutive digits for the encoding circuit.

Assignments (2)
CHANGE OF NAME Recorded May 7, 2007
From: APPLE COMPUTER, INC.
To: APPLE INC.
Reel/Frame 019265/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2001
From: ATHAS, WILLIAM C.
To: APPLE COMPUTER, INC.
Reel/Frame 012324/0041 →