Semiconductor device
View Patent ↗A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing. As a result, it is possible to provide a semiconductor device capable of generating a side tone without increasing the magnitude of a load borne by a CPU and without requiring an external circuit component.
1. A semiconductor device formed on a single semiconductor chip, comprising:
a digital-signal-processing circuit;
a CPU controlling said digital-signal-processing circuit: and
an interface circuit inputting a digital signal synchronously with a first clock signal and supplying said input digital signal to said digital-signal-processing circuit and outputting digital data processed by said digital-signal-processing circuit synchronously with said first clock signal,
wherein said interface circuit includes:
an input circuit inputting said digital signal synchronously with said first clock signal and supplying said input digital signal to said digital-signal-processing circuit;
a gain-adjusting circuit adjusting a gain of said digital signal supplied to said input circuit; and
an output circuit adding said digital signal with said gain thereof adjusted to a digital signal supplied from said digital-signal-processing circuit and outputting a resulting digital signal synchronously with said first clock signal;
wherein said input circuit comprises:
an input shift register inputting and shifting the digital signal synchronously with said first clock signal; and
an input register latching the digital signal shifted in said input shift register synchronously with a second clock signal.
2. A semiconductor device according to claim 1 , wherein said gain-adjusting circuit comprises:
a shifter for inputting and shifting the digital signal inputted and shifted by said input shift register; and
a gain control register controlling the number of shift operations carried out by said shifter.
3. A semiconductor device according to claim 2 , wherein said output circuit comprises:
an output register latching the digital signal processed by said digital-signal processing unit synchronously with said second clock signal;
an adder adding a signal output by said shifter to said latched digital data in said output register; and
an output shift register inputting a signal output by said adder and shifting and outputting said signal synchronously with said first clock signal.
4. A semiconductor device according to claim 2 , wherein said CPU is configured to access said gain control register to write data into said gain control register.
5. A semiconductor device according to claim 3 , wherein said CPU is configured to access said input register and said output register to write data into said input and output registers.
6. A semiconductor device according to claim 3 , wherein:
an output stage of said input register and an output stage of said output register are each provided with a changeover switch selecting either said output stage or a value of 0;
select control information for driving said changeover switches is stored in a switch control register; and
said CPU is configured to access said switch control register to write data into said switch control register.
7. A semiconductor device according to claim 1 , wherein, in response to an interrupt signal, said CPU issues a command to said digital-signal-processing circuit, requesting said digital-signal-processing circuit to carry out processing operations.