Clock domain crossing FIFO
View Patent ↗A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
1. A method of passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the method comprising:
linking write-address information with data in the source clock domain;
generating a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
transmitting the data with the linked write-address information and the transmit clock signal to the receive clock domain;
writing the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal; and
reading the data from the storage element synchronized with the receive clock;
wherein the data is N bits wide and the storage element is M locations deep, and the data with the linked write-address information is communicated using at most N+2*┌log 2 (M)┐+4 electrical signal paths, M being a power of 2.
2. A method of passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the method comprising:
linking write-address information with data in the source clock domain;
generating a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
transmitting the data with the linked write-address information and the transmit clock signal to the receive clock domain;
writing the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal; and
reading the data from the storage element synchronized with the receive clock;
wherein the data is N bits wide and the storage element is M locations deep, and the data with the linked write-address information is communicated using at most N+3*┌log 2 (M)┐+4 electrical signal paths, M not being a power of 2.
3. A circuit arrangement for passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the circuit arangememt comprising:
means for linking write-address information with data in the source clock domain;
means for generating a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
means for transmitting the data with the linked write-address information and the transmit clock signal to the receive clock domain;
means for writing the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal;
means for reading the data from the storage element synchronized with the receive clock; and
at most N+P*┌log 2 (M)┐+4 electrical signal paths coupled between the source and receive clock domains for communicating the data with the linked write-address information, wherein the data is N bits wide, the storage element is M locations deep, and P is 2 when M is a power of 2 and is 3 when M is not a power of 2.
4. A circuit arrangement for passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the circuit arrangement comprising:
means for linking write-address information with data in the source clock domaim;
means for generating a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
means for transmitting the data with the linked write-address information and the transmit clock signal to the receive clock domain;
means for writing the data at an address designating a storage element, the designated address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal;
means for reading the data from the storage element synchronized with the receive clock; and
at most N+P*┌log 2 (M)┐+4 electrical signal paths coupled between the source and receive clock domains for communicating the data with the linked write-address information, wherein the data is N bits wide, the storage element is M locations deep, and P is 2 when M is a power of two and is 3 when M is not a power of two; and means for disabling the transmit clock signal during periods when the means for transmitting is not transmitting the data with the linked write-address information.
5. A circuit arrangement for passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the circuit arrangement comprising:
a first clock generator adapted to generate a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
a first processing circuit adapted to link write-address information with data in the source clock domain and to transmit the data with the linked write-address information and the transmit clock signal to the receive clock domain;
a second processing circuit in the receive clock domain adapted to write the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal;
the second processing circuit being further adapted to read the data from the storage element synchronized with the receive clock; and
at most N+2*┌log 2 (M)┐+4 electrical signal paths coupled between the first and second processing circuits for communicating the data with the linked write-address information, wherein the data is N bits wide, the storage element is M locations deep, and M is a power of 2.
6. A circuit arrangement for passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the circuit arrangement comprising:
a first clock generator adapted to generate a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
a first processing circuit adapted to link write-address information with data in the source clock domain and to transmit the data with the linked write-address information and the transmit clock signal to the receive clock domain;
a second processing circuit in the receive clock domain adapted to write the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal;
the second processing circuit being further adapted to read the data from the storage element synchronized with the receive clock; and
at most N+3*┌log 2 (M)┐+4 electrical signal paths coupled between the first and second processing circuits for communicating the data with the linked write-address information, wherein the data is N bits wide, the storage element is M locations deep, and M is not a power of 2.
7. A circuit arrangement for passing data from a source clock domain to a receive clock domain, the source and receive clock domains respectively using non-synchronous source and receive clocks, the circuit arrangement comprising:
a first clock generator adapted to generate a transmit clock signal in the source clock domain, the transmit clock signal being synchronous with the source clock;
a first processing circuit adapted to link write-address information with data in the source clock domain and to transmit the data with the linked write-address information and the transmit clock signal to the receive clock domain;
a second processing circuit in the receive clock domain adapted to write the data at an address designating a storage element, the address corresponding to the linked write-address information, the storage element being located in the receive clock domain and the data being clocked into the storage element synchronous with the transmit clock signal;
the second processing circuit being further adapted to read the data from the storage element synchronized with the receive clock; and
at most N+p*┌log 2 (M)┐+4 electrical signal paths coupled between the first and second processing circuits for communicating the data with the linked write-address information, wherein the data is N bits wide, the storage element is M locations deep, and P is 2 when the storage element has a depth that is a power of two and is 3 when the storage element has a depth that is not a power of two; and a circuit adapted to disable the transmit clock signal during periods when the first processing circuit is not transmitting the data with the linked write-address information.