Differential drive circuit and method for generating an a.c. differential drive signal

1. A differential drive circuit for generating a differential drive signal for driving a liquid crystal device, the differential drive signal having a root mean square value defined by a digital input value and including a first differential component and a second differential component, the circuit comprising:

first differential component generating means for counting a clock signal to generate successive values of a periodic count, each of the values including a most-significant bit, and for generating the first differential component of the differential drive signal in response to successive ones of the most-significant bit of the count;

second differential component generating means for generating the second differential component of the differential drive signal in response to the digital input value and the successive values of the count, wherein the differential drive signal drives the liquid crystal device, and wherein each of the first differential component and the second differential component has a respective waveform; and

at least one of the differential component generating means includes:

means for generating a respective synchronizing signal differing in phase from the differential component generated by the other of the differential component generating means by a phase difference defined by the digital input value, and

differential component waveform generating means, operating in response to the synchronizing signal, for defining the waveform of the respective differential component.

2. The differential drive circuit of claim 1 , in which:

the successive values of the count range from a lower bound to an upper bound; and

the most-significant bit of the count changes state each time the count resets to the lower bound.

3. The differential drive circuit of claim 2 , in which the lower bound is zero.

4. The differential drive circuit of claim 1 , in which the second differential component generating means includes a digital phase shifter operating in response to the digital input value and the count.

5. The differential drive circuit of claim 1 , in which:

the digital input value is a Gray code value; and

the count is a Gray code count.

6. The differential drive circuit of claim 1 , in which the differential component waveform generating means includes:

a baseline signal generator that generates a baseline signal; and

an adder configured to add the baseline signal to the synchronizing signal to generate the respective differential component.

7. The differential drive circuit of claim 1 , in which the differential component waveform generating means includes an amplifier operating to amplify the synchronizing signal to generate the respective differential component.

8. The differential drive circuit of claim 1 , in which the differential component waveform generating means includes means, operating in response to the synchronizing signal, for generating the respective differential component with an amplitude different from that of the differential component generated by the other of the differential component generating means.

9. The differential drive circuit of claim 1 , in which the differential component waveform generating means includes means, operating in response to the synchronizing signal, for generating the respective differential component with a duty cycle different from that of the synchronizing signal.

10. The differential drive circuit of claim 1 , in which:

the differential component generated by one of the differential component generating means alternates between a first voltage and a second voltage, the first voltage and the second voltage having a first difference and a first average voltage; and

the differential component waveform generating means includes means, operating in response to the synchronizing signal, for alternating the differential component generated by the other of the differential component generating means between a third voltage and a fourth voltage, the third voltage and the fourth voltage having a second difference and a second average voltage, the second difference differing symmetrically from the first difference to define the amplitude of a baseline a.c. component of the differential drive signal, the second average voltage differing from the first average voltage to define the level of a DC component of the differential drive signal.

11. The differential drive circuit of claim 1 , in which the differential component waveform generating means is for defining the waveform of the respective one of the differential components in at least one of frequency, amplitude, average voltage, duty cycle and shape.

12. The differential drive circuit of claim 1 , in which the first differential component generating means is additionally for outputting the successive ones of the most-significant bit of the count as the first differential component.

13. A method for generating a differential drive signal for driving a liquid crystal device, the differential drive signal having a root mean square value defined by a digital input value, and including a first differential component and a second differential component, the method comprising:

providing a clock signal;

counting the clock signal to generate successive values of a periodic count, the values each including a most-significant bit;

changing the state of the first differential component of the differential drive signal when the count reaches a predefined starting value;

changing the state of the second differential component of the differential drive signal when the count has a predetermined relationship to the digital input value, wherein the differential drive signal drives the liquid crystal device, each of the first differential component and the second differential component having a respective waveform;

generating a synchronizing signal corresponding to one of the differential components and differing in phase from the other of the differential components by a phase difference defined by the digital input value; and

defining the waveform of the one of the differential components in response to the synchronizing signal.

14. The method of claim 13 , in which the predetermined relationship is equality.

15. The method of claim 13 , in which the predetermined relationship is a difference of one least-significant bit.

16. The method of claim 13 , in which the predetermined starting value is zero.

17. The method of claim 13 , additionally comprising outputting successive ones of the most-significant bit as the first differential component.

18. The method of claim 17 , in which changing the state of the second differential components includes digitally shifting the phase of successive ones of the most-significant bit of the count by a phase difference defined by the digital input value.

19. The method of claim 13 , in which:

the digital input value is a Gray code value; and

in counting the clock signal, the successive values of the count are each a Gray code value.

20. The method of claim 13 , in which defining the waveform of the one of the differential components includes generating the one of the differential components with a waveform differing from a square wave.

21. The method of claim 13 , in which defining the waveform of the one of the differential components includes adding a baseline signal to the synchronizing signal.

22. The method of claim 13 , in which defining the waveform of the one of the differential components includes amplifying the synchronizing signal.

23. The method of claim 13 , in which:

the other of the differential components alternates between a first voltage and a second voltage; and

defining the waveform of the one of the first differential components includes alternating the one of the differential components between a third voltage and a fourth voltage in response to the synchronizing signal corresponding to the one of the differential components, the third voltage and the fourth voltage differing substantially symmetrically from the first voltage and the second voltage, respectively.

24. The method of claim 13 , in which:

the other of the differential components alternates between a first voltage and a second voltage, the first voltage and the second voltage having a first average voltage; and

defining the waveform of the one of the first differential components includes alternating the one of the differential components between a third voltage and a fourth voltage in response to the synchronizing signal corresponding to the one of the differential components, the third voltage and the fourth voltage having a second average voltage, different from the first average voltage.

25. The method of claim 13 , in which defining the waveform of the one of the differential components includes generating the one of the differential components with a duty cycle different from that of the synchronizing signal corresponding to the one of the differential components.

26. The method of claim 13 , in which changing the state of the second differential component includes:

providing a digital input value selected from a palette of digital input values;

generating a digital sequence of palette codes synchronized with the count; and

changing the state of the second differential component in response to a predetermined relationship between the palette code and the digital sequence.