Phase detector circuit for a phase control loop
View Patent ↗A phase detector circuit for a phase control loop includes two EXOR circuits and an integrating loop filter which are connected to form one circuit. The two EXOR circuits have common load resistors or current sources. The output signals from the EXOR circuits are integrated through the use of two integrators, which are respectively connected in parallel with the common load resistors or current sources. The voltage across the two integrators provides the output voltage of the loop filter. This eliminates the need for an additional differential amplifier and integrator. The phase detector has a low current consumption and can be produced with a simplified circuit technique.
1. A phase detector circuit for a phase control loop, comprising:
an input connection for receiving input data;
a data regeneration circuit operatively connected to said input connection, said data regeneration circuit regenerating the input data in dependence of a clock signal;
two EXOR circuits connected to said data regeneration circuit, said EXOR circuits operating as phase comparators;
an integrating loop filter connected to said two EXOR circuits such that said two EXOR circuits and said integrating loop filter are connected to form one circuit, said integrating loop filter integrating a difference between signals provided by said two EXOR circuits and said integrating loop filter providing an output signal controlling a generation of the clock signal fed back to said data regeneration circuit;
said two EXOR circuits having common circuit elements selected from the group consisting of load resistors and current sources;
two integrators respectively connected in parallel to said common circuit elements, said two integrators integrating output signals provided by said two EXOR circuits; and
said integrating loop filter providing, as the output signal, a voltage resulting at said two integrators.
2. The phase detector circuit according to claim 1 , wherein said common circuit elements selected from the group consisting of the load resistors and the current sources are high-impedance elements such that said common circuit elements, in conjunction with said integrators, provide an integrating action.
3. The phase detector according to claim 1 , wherein said integrators each include a series circuit and a capacitance provided in parallel to said series circuit, said series circuit includes a resistor and a further capacitance.
4. The phase detector according to claim 1 , including:
a current mirror circuit operatively connected to said common circuit elements; and
said common circuit elements being embodied as said current sources, said current mirror circuit setting a current flowing through said current sources.
5. The phase detector according to claim 1 , including:
a current source transistor operatively connected to said common circuit elements; and
said common circuit elements being embodied as said load resistors, said current source transistor setting a current flowing through said load resistors.
6. The phase detector according to claim 1 , wherein said data regeneration circuit includes two D-flip-flop circuits connected to said two EXOR circuits, said two D-flip-flop circuits having respective data inputs and clock inputs.
7. In combination with a phase locked loop circuit, a phase detector circuit, comprising:
an input connection for receiving input data;
a data regeneration circuit operatively connected to said input connection, said data regeneration circuit regenerating the input data in dependence of a clock signal;
two EXOR circuits connected to said data regeneration circuit, said EXOR circuits operating as phase comparators;
an integrating loop filter connected to said two EXOR circuits such that said two EXOR circuits and said integrating loop filter are connected to form one circuit, said integrating loop filter integrating a difference between signals provided by said two EXOR circuits and said integrating loop filter providing an output signal controlling a generation of the clock signal fed back to said data regeneration circuit;
said two EXOR circuits having common circuit elements selected from the group consisting of load resistors and current sources;
two integrators respectively connected in parallel to said common circuit elements, said two integrators integrating output signals provided by said two EXOR circuits; and
said integrating loop filter providing, as the output signal, a voltage resulting at said two integrators.
8. In combination with a delay locked loop circuit, a phase detector circuit, comprising:
an input connection for receiving input data;
a data regeneration circuit operatively connected to said input connection, said data regeneration circuit regenerating the input data in dependence of a clock signal;
two EXOR circuits connected to said data regeneration circuit, said EXOR circuits operating as phase comparators;
an integrating loop filter connected to said two EXOR circuits such that said two EXOR circuits and said integrating loop filter are connected to form one circuit, said integrating loop filter integrating a difference between signals provided by said two EXOR circuits and said integrating loop filter providing an output signal controlling a generation of the clock signal fed back to said data regeneration circuit;
said two EXOR circuits having common circuit elements selected from the group consisting of load resistors and current sources;
two integrators respectively connected in parallel to said common circuit elements, said two integrators integrating output signals provided by said two EXOR circuits; and
said integrating loop filter providing, as the output signal, a voltage resulting at said two integrators.