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App. No. 10/001,796 · Confirmation No. 2300

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING THE SAME

Inventor: Hirotaka Shimoda
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
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 Code Description Pages PDF
2003-08-06 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-08-06 LET. Miscellaneous Incoming Letter 1 View
2001-12-05 TRNA Transmittal of New Application 2 View
2001-12-05 ADS Application Data Sheet 1 View
2001-12-05 A.PE Preliminary Amendment 4 View
2001-12-05 SPEC Specification 22 View
2001-12-05 CLM Claims 3 View
2001-12-05 ABST Abstract 1 View
2001-12-05 DRW Drawings-only black and white line drawings 6 View
2001-12-05 OATH Oath or Declaration filed 2 View
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Quick Facts
App. No.
10/001,796
Filed
2001-12-05
Granted
2003-10-21
Pub. No.
US20020101249A1
Art Unit
2854
PTA
-31 days