IP Library Granted Patent US 6,928,599
Granted Patent B2
US 6,928,599 · App. 10/002,405 · Granted Aug 9, 2005

Method and apparatus for decoding data

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Quick Facts
Patent No.
US 6,928,599
App. No.
10/002,405
Granted
Aug 9, 2005
Kind
B2
Abstract

Decoding an encoded block of data is accomplished by partitioning the block into a first and a second sub-block and performing forward and backward iterative calculations on the sub-blocks in separate processes. Based on results of the iterative calculations an output matrix may be calculated for each sub-block. The outputs may be combined.

Claims (50)

1. A method of decoding an encoded block of data comprising:

partitioning the block into a first and a second sub-block assigned to a first and second process respectively; and

performing backward iterative calculations on the first sub-block within some point of a second portion of the second sub-block based on results from backward iterative calculations on a first portion of the second sub-block.

2. The method according to claim 1 , further comprising:

performing forward iterative calculations on the first sub-block.

3. The method according to claim 2 , further comprising: calculating a first output based on the results of the forward and backward iterative calculations performed on the first sub-block.

4. The method according to claim 3 , further comprising:

performing forward and backward iterative calculations on the second sub-block and calculating a second output based on the results of the forward and backward iterative calculations on the second block.

5. The method according to claim 4 , further comprising:

combining the first and second outputs into a single data black.

6. The method according to claim 4 , further comprising:

storing the results of the iterative calculation of the second sub-block on a temporary memory on which results from the iterative calculation of the first sub-block are stored.

7. The method according to claim 6 , wherein results from the iterative calculations on the second sub-block are stored to a portion of the temporary memory after an output based on results stored in that portion of memory is calculated.

8. A decoder comprising:

a processing unit to start to perform a backward iterative calculation on a first sub-block within some point of a second portion of the second sub-block, based on results of a backward iterative calculation performed by a second processing unit on a first portion of a second sub-block.

9. The decoder according to claim 8 , wherein said processing unit is adapted to perform forward iterative calculations on the first sub-block.

10. The decoder according to claim 9 , wherein said processing unit is adapted to calculate an output for the first sub-block based on the forward and backward iterative calculations for the sub-block.

11. The decoder according to claim 10 , wherein said second processing unit is to perform backward and forward iterative calculations of the second sub-block and to calculate an output for the second sub-block based on results from the forward and backward calculations on the second sub-block.

12. The decoder according to claim 11 , wherein the processing unit comprises:

a forward iterative calculator, a backward iterative calculator and an output calculator.

13. The decoder according to claim 12 , further comprising:

a temporary memory.

14. The decoder according to claim 13 , wherein said temporary memory is configured to store the results of iterative calculations on a first sub-block and then the results of iterative calculations on a second sub-block.

15. The decoder according to claim 14 , wherein portions of said temporary memory are freed up as an output of the first sub-block is calculated.

16. The decoder according to claim 15 , wherein results from iterative calculations on the second sub-block are stored in the freed portion of said temporary memory.

17. An apparatus comprising:

a data block parser to parse an encoded data block into at least first and second sub-blocks;

at least first and second processing units to perform forward and backward decoding at least on the first and second sub-blocks, respectively, of the encoded data block wherein, the backward decoding of the first sub-block is able to start within iterative calculations of the second sub-black; and

a memory to store outputs of at least the first and second processing units.

18. The apparatus of claim 17 , wherein the first processing unit is able to perform a backward iterative calculation on at least a portion of the first sub-block based on results of a backward iterative calculation performed by the second processing unit on at least a portion of the second sub-block.

19. The apparatus of claim 18 , wherein the first processing unit is able to perform forward iterative calculations on at least a portion of the first sub-block.

20. The apparatus of claim 19 , wherein the first processing unit is able to decode the first sub-block and to provide an output based on the forward and backward iterative calculations preformed on the first sub-block.

21. The apparatus of claim 18 , wherein the second processing unit is able to perform backward and forward iterative calculations of the second sub-block and to provide an output based on results from the forward and backward calculations preformed on the second sub-block.

22. The apparatus of claim 17 , wherein the memory is able to store the results of the iterative calculations preformed on the first sub-block and the results of the iterative calculations preformed on the second sub-block.

23. The apparatus of claim 22 , wherein portions of the memory are freed up as an output of the first sub-block is calculated.

24. The apparatus of claim 23 , wherein results output from iterative calculations on the second sub-block are stored in the freed up portions of the memory.

25 .The apparatus of claim 17 , wherein the first and second sub-blocks are partitioned into two or more sub-block segments.

26. The apparatus of claim 25 , wherein at least some of the sub-block segments are decoded by a separate thread and/or separate process running on one of the processing unit.

27. The apparatus of claim 25 , wherein at least some of the sub-block segments are decoded by a separate thread and/or separate process running on a digital signal processor.

28. A method comprising:

parsing an encoded data block into first and second sub-blocks; and

performing a forward and backward decoding on the first and second sub-blocks by decoders of first and second processing units wherein, the backward decoding of the first sub-block is able to start within iterative calculations of a portion of the second sub-block.

29. The method of claim 28 , further comprising:

performing a backward iterative calculation an the first sub-block based on results of a backward iterative calculation performed on at least a portion of the second sub-block.

30. The method of claim 28 , wherein performing a forward and backward decoding on the first and second sub-blocks comprises decoding sub-block segments by a separate thread and/or separate process.

31. The method of claim 28 , further comprising:

storing the results output from iterative calculations on a first sub-block and the results output from iterative calculations on a second block.

32. The method of claim 31 , wherein storing comprises:

freeing up portions of a memory as an output of the first sub-block is calculated; and

storing results output from iterative calculations on the second sub-block in the freed up portion of the memory.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2006
From: DSPC TECHNOLOGIES LTD.
To: INTEL CORPORATION
Reel/Frame 018498/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2003
From: D.S.P.C. TECHNOLOGIES LTD.
To: INTEL CORPORATION
Reel/Frame 014047/0317 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2002
From: EDLIS, OPHIR; LEVY, SHARON; SCHWARTZ, EREZ; MAZUZ, GADI; DEITCHER, DAVID; MIZRAHI, NOAM
To: D.S.P.C. TECHNOLOGIES LTD.
Reel/Frame 013443/0343 →