Granted Patent
Utility
US 6,578,183
· Confirmation No. 4704
METHOD FOR GENERATING A PARTITIONED IC LAYOUT
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-10-22 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-10-22 | SPEC |
Specification | 14 | View | |
| 2001-10-22 | CLM |
Claims | 8 | View | |
| 2001-10-22 | ABST |
Abstract | 1 | View | |
| 2001-10-22 | DRW |
Drawings-only black and white line drawings | 3 | View | |
| 2001-10-22 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Kit-Lam Cheong
Palo Alto, CA
Wei-Jin Dai
Cupertino, CA
Hsi-Chuan Chen
Fremont, CA
Patrick John Eichenseer
Austin, TX
Attorneys & Agents of Record
Classification
USPC
716/7
G06F30/392
Prosecution
- Examiner
- GARBOWSKI, LEIGH M
- Art Unit
- 2825
- Customer No.
- 7812
- Docket No.
- SILI 2280
- Confirmation No.
- 4704
Publication
- Pub. No.
- US20030079192A1
- Pub. Date
- 2003-04-24
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-07-08
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-10-22
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Quick Facts
- Patent No.
- US 6,578,183
- App. No.
- 10/003,932
- Filed
- 2001-10-22
- Granted
- 2003-06-10
- Pub. No.
- US20030079192A1
- Examiner
- GARBOWSKI, LEIGH M
- Art Unit
- 2825
- PTA
- 0 days
External Links