Bi-directional bus bridge in which multiple devices can assert bus concurrently
View Patent ↗A bridge device couples together two buses in which more than one device at a time can assert a bus signal. The bridge includes comparators to drive or assert signals on one bus only if the signal is being asserted by the corresponding signal on the other of said buses. That is, the bridge does not drive a signal on a bus that is already being actively driven by a device coupled to that same bus. However, if a device coupled to the other of the buses drives the signal, then the comparator does drive the signal. The bridge preferably includes one such comparator for each bus signal on both buses. The bridge is particularly well-suited for use in bridging I 2 C buses.
1. A computer system, comprising:
a host processor;
an input device coupled to said host processor; and
a bridge coupled to said host processor, said bridge couples together a first bus and a second bus;
wherein said bridge drives a signal on the first bus if said signal is being actively driven by a device coupled to the second bus, but not if said signal is only being actively driven by a device coupled to the first bus and wherein said bridge includes a comparator to drive said signal, said comparator has one input coupled to a threshold and another input coupled to the signal from both the first and the second bus.
2. The computer system of claim 1 wherein said threshold is set at a level between the level at which a device on the first bus would cause said signal to be driven to and the level at which a device on the second bus would cause said signal to be driven to.
3. The computer system of claim 1 wherein said bridge includes a comparator for each signal on each of said first and second buses, each comparator used to drive a signal on one of the buses if such signal is being actively driven by a device coupled to the other of said buses, but not if the signal is only being driven by a device coupled to the bus having the signal being driven by the comparator.
4. The computer system of claim 3 wherein the bridge includes a logic gate coupled to each comparator, said logic capable of being disabled by an enable signal to disable the bridging function of the bridge.
5. The computer system of claim 3 wherein said bridge includes a resistor which causes the voltage level of a signal actively driven by a device coupled to the first bus to be different than when that same signal is actively driven by a device coupled to the second bus.
6. The computer system of claim 1 wherein said first and second buses comprise buses on which more than one device can actively and concurrently drive a signal on the buses.
7. The computer system of claim 1 wherein said first and second buses comprise I 2 C buses.
8. A bridge device coupling together a first bus and a second bus, each bus having a plurality of bus signals that are similar to bus signals found on the other bus and each bus being capable of being coupled to a bus device, comprising:
a plurality of comparators, each of the plurality of comparators having a first input and a second input, a threshold voltage coupled to the first input of each of the plurality of comparators and the second input of each of the plurality of comparators is coupled to a one of the plurality of similar bus signals from both said first and second bus.
9. The bridge device of claim 8 wherein each comparator causes a signal on one of the buses to be driven if that signal is being actively driven by a bus device coupled to the other of said buses, but not if the signal is only being actively driven by a bus device coupled to the bus having the signal being driven by the comparator.
10. The bridge device of claim 8 wherein said threshold voltage of each comparator is set at a level between the level at which a bus device on the first bus would cause said one of the plurality of similar bus signals to be driven to and the level at which a bus device on the second bus would cause said one of the plurality of similar bus signals to be driven to.
11. The bridge device of claim 8 wherein the bridge includes a logic gate coupled to each comparator, said logic gate capable of being disabled by an enable signal to disable the bridging function of the bridge.
12. The bridge device of claim 8 wherein said first and second buses comprise buses on which more than one device can actively and concurrently drive a signal on the buses.
13. The bridge device of claim 8 wherein said first and second buses comprise I 2 C buses.
14. A method of bridging two buses together, comprising:
(a) comparing the voltage level of a bus signal coupled to both buses to a threshold level;
(b) determining which bus is actively driving said bus signal; and
(c) asserting said bus signal on one of the buses if such signal is being actively driven by the other of said buses.
15. The method of claim 14 wherein said buses include a plurality of signals and (a), (b) and (c) are performed for each of said signals.
16. The method of claim 14 wherein said buses comprise I 2 C buses.
17. A computer system, comprising:
a host processor; and
a bridge coupled to said host processor, said bridge couples together a first bus and a second bus, said bridge including a plurality of cross-coupled comparator units that determine whether the first or second bus is actively asserting a bus signal and driving said signal on the other of said first or second buses.
18. A bridge interconnecting two buses including a plurality of cross-coupled comparator units that determine which bus is actively driving a bus signal or whether both buses are actively driving said bus signal.