System design verification using selected states of a processor-based system to reveal deficiencies
View Patent ↗The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.
1. A method for determining one or more error conditions in a system, comprising:
operating a device in the system in a first state;
modifying at least one operational characteristic of the device to operate in a second state by adjusting a number of transaction identifiers that are available to the device during the second state;
determining if an error condition occurs in the system in response to modifying the operational characteristic of the device.
2. A method for determining one or more error conditions in a system, comprising:
operating a device in the system in a first state;
modifying at least one operational characteristic of the device to operate in a second state by adjusting a number of target identifiers that are available to the device during the second state;
determining if an error condition occurs in the system in response to modifying the operational characteristic of the device.
3. A method for determining one or more error conditions in a system, comprising:
operating a device in the system in a first state;
modifying at least one operational characteristic of the device to operate in a second state by adjusting at least one of a number of secondary transfer buffer transactions, victim rewrite buffer transactions, and slave broadcast invalidates that are available during a preselected interval;
determining if an error condition occurs in the system in response to modifying the operational characteristic of the device.
4. A system, comprising:
a control unit adapted to provide a control signal;
a first device adapted to generate one or more requests; and
a second device adapted to process one or more requests from the first device using a first configuration and adapted to process one or more requests using a second configuration in response to receiving the control signal;
wherein the first configuration of the second device comprises a preselected number of available transaction identifiers and wherein the second configuration comprises less than the preselected number of available transaction identifiers.
5. A system, comprising:
a control unit adapted to provide a control signal;
a first device adapted to generate one or more requests; and
a second device adapted to process one or more requests from the first device using a first configuration and adapted to process one or more requests using a second configuration in response to receiving the control signal;
wherein the first configuration of the second device comprises a preselected number of available target identifiers and wherein the second configuration comprises less than the preselected number of available target identifiers.
6. An article comprising one or more machine-readable storage media containing instructions that when executed enable a processor to:
operate a device in the system in a first state;
modify at least one operational characteristic of the device to operate in a second state by adjust adjusting a number of transaction identifiers that are available to the device during the second state; and
determine if an error condition occurs in the system in response to modifying the operational characteristic of the device.
7. An article comprising one or more machine-readable storage media containing instructions that when executed enable a processor to:
operate a device in the system in a first state;
modify at least one operational characteristic of the device to operate in a second state by adjusting a number of target identifiers that are available to the device during the second state; and
determine if an error condition occurs in the system in response to modifying the operational characteristic of the device.
8. An apparatus, comprising:
an interface; and
a verification module adapted to receive a control signal from the interface in a first state and to adjust an operating characteristic of the apparatus to exercise a system in a second state such that the verification module is capable of revealing one or more error conditions in the system in response to receiving the control signal;
wherein the verification module reduces the number of transactions that may be processed by the apparatus for a preselected interval by reducing a number of transaction identifiers that are available to a device during the second state.
9. An apparatus, comprising:
an interface; and
a verification module adapted to receive a control signal from the interface in a first state and to adjust an operating characteristic of the apparatus to exercise a system in a second state such that the verification module is capable of revealing one or more error conditions in the system in response to receiving the control signal;
wherein the verification module increases the number of transactions that may be processed by the apparatus for a preselected interval by increasing a number of transaction identifiers that are available to a device during the second state.