Method and circuit for synchronizing a receiver for a convolutionally coded reception signal
View Patent ↗A method for synchronizing a receiver for a convolutionally coded reception signal having a sequence of received data symbols includes decoding the convolutionally coded reception signal by means of a Viterbi decoder that calculates a minimum metric signal sequence. The metric signal sequence is then compared with an adjustable threshold value. If metric signal exceeds the threshold value too frequently during a predetermined time period, at least one received data symbol is discarded.
1. A method for synchronizing a receiver for a convolutionally coded reception signal having a sequence of received data symbols, said method comprising:
decoding the convolutionally coded reception signal by means of a Viterbi decoder that calculates a minimum metric signal sequence;
comparing the signal values of the metric signal sequence with an adjustable threshold value; and
discarding at least one received data symbol if the threshold value is exceeded too frequently by the metric signal sequence during a predetermined time period.
2. The method as claimed in claim 1 , further comprising selecting the received data symbols to be quadrature amplitude modulation data symbols.
3. The method as claimed in claim 1 , further comprising selecting the received data symbols from the group consisting of 64-quadrature amplitude modulation data symbols and 256-quadrature amplitude modulation data symbols.
4. A synchronization circuit for a signal receiver for receiving a convolutionally coded reception signal which is composed of a sequence of data symbols, having:
a switching device for switching the received convolutionally coded data symbols;
a Viterbi decoder for decoding the switched-through data symbols, the Viterbi decoder calculating a minimum metric signal sequence of the reception signal;
a first comparator circuit for comparing the signal values of the calculated metric signal sequence with an adjustable threshold value;
a counter which counts the number of occasions the threshold value is exceeded;
a second comparator circuit for comparing the counter reading of the counter with an adjustable counter threshold value, the second comparator circuit actuating the switching device to suppress a received data symbol when the counter threshold value is exceeded.
5. The synchronization circuit as claimed in claim 4 , wherein the reception signal is a quadrature amplitude modulation reception signal.
6. A synchronization circuit for a signal receiver configured to receive a convolutionally coded reception signal having of a sequence of data symbols, said circuit comprising:
a switching device for providing switched-through data symbols by switching the sequence of data symbols;
a Viterbi decoder configured to receive the switched-through data symbols from the switching device and to decode the switched-through data symbols, the Viterbi decoder providing a minimum metric signal sequence of the reception signal;
a first comparator circuit for comparing the signal values of the calculated metric signal sequence with an adjustable threshold value;
a counter that maintains a counter reading indicative of the number of times the adjustable threshold value is exceeded; and
a second comparator circuit for comparing the counter reading with an adjustable counter threshold value; and
a second comparator circuit for comparing the counter reading with an adjustable counter threshold value, the second comparator circuit being configured to cause the switching device to suppress a received data symbol when the counter threshold value is exceeded.
7. The synchronization circuit as claimed in claim 6 , wherein the signal receiver is configured to receive, as the reception signal, a quadrature amplitude modulation reception signal.