Receiver circuit for a communications terminal and method for processing signals in a receiver circuit
View Patent ↗A receiver circuit for a communications terminal includes a signal pre-processing circuit having: an analog/digital converter device with K analog/digital converters connected in parallel, a conversion device, and a filter device connected downstream of the conversion device. The filter device has N digital filters connected in parallel, where N is an integer that is greater than or equal to 1 and is less than K.
1. A receiver circuit for a communications terminal, comprising:
a signal-receiving device providing K analog reception signals, K being greater than one; and
a signal pre-processing circuit configured downstream from said signal-receiving device;
said pre-processing circuit including:
an analog/digital converter device having K analog/digital converters connected in parallel for sampling the K reception signals independently of one another with a sufficient sampling rate and for providing K digital signals;
a multiplexer for multiplexing the K digital signals and outputting at least one multiplexer output signal formed from the K multiplexed signals; and
a digital filter device for filtering the at least one multiplexer output signal, said digital filter device having memory elements formed by shift registers of length K, and said digital filter device including:
a plurality of single digital filters; and
sampling rate reduction circuits configured in series in an alternating fashion.
2. The receiver circuit according to claim 1 , wherein said digital filter device has an order of magnitude L between 5 and 20.
3. The receiver circuit according to claim 1 , wherein said digital filter device has an order of magnitude L between 10 and 18.
4. The receiver circuit according to claim 1 , wherein:
said signal-receiving device includes a single reception sensor outputting a single sensor reception signal; and
the K reception signals are generated by splitting the reception signal.
5. The receiver circuit according to claim 1 , wherein:
said signal-receiving device includes a single reception sensor outputting a single sensor reception signal; and
the K reception signals are generated by splitting the reception signal into an in-phase reception signal and a quadrature reception signal.
6. The receiver circuit according to claim 1 , wherein said signal-receiving device includes a plurality of reception sensors, each of said plurality of said reception sensors has a directional reception characteristic for sensing radio signals in a predefined spatial segment.
7. A mobile station of a mobile radio system, comprising:
a signal-receiving device providing K analog reception signals, K being greater than one; and
a signal pre-processing circuit configured downstream from said signal-receiving device;
said pre-processing circuit including:
an analog/digital converter device having K analog/digital converters connected in parallel for sampling the K reception signals independently of one another with a sufficient sampling rate and for providing K digital signals;
a multiplexer for multiplexing the K digital signals and outputting at least one multiplexer output signal formed from the K multiplexed signals; and
a digital filter device for filtering the at least one multiplexer output signal, said digital filter device having memory elements formed by shift registers of length K, and said digital filter device including:
a plurality of single digital filters; and
sampling rate reduction circuits configured in series in an alternating fashion.
8. A receiver circuit for a communications terminal, comprising:
a signal-receiving device providing K analog reception signals, K being greater than one; and
a signal pro-processing circuit configured downstream from said signal-receiving device;
said pre-processing circuit including:
an analog/digital converter device having K analog/digital converters connected in parallel for sampling the K reception signals independently of one another with a sufficient sampling rate and for providing K digital signals;
a stage containing K digital zero-inserting elements that are connected in parallel, each of said zero-inserting elements being fed with a respective one of the K digital signals and inserts K−1 zeros per sampling value of the respective one of the K digital signals into the respective one of the K digital signals; and
a digital filter device for filtering the K digital signals with inserted zeros, said digital filter device having memory elements formed by shift registers of length K, and said digital filter device including:
a plurality of single digital filters; and
sampling rate reduction circuits configured in series in an alternating fashion.
9. The receiver circuit according to claim 8 , wherein said digital filter device has an order of magnitude L between 5 and 20.
10. The receiver circuit according to claim 8 , wherein said digital filter device has an order of magnitude L between 10 and 18.
11. The receiver circuit according to claim 8 , wherein:
said signal-receiving device includes a single reception sensor outputting a single sensor reception signal; and
the K reception signals are generated by splitting the reception signal.
12. The receiver circuit according to claim 8 , wherein:
said signal-receiving device includes a single reception sensor outputting a single sensor reception signal; and
the K reception signals are generated by splitting the reception signal into an in-phase reception signal and a quadrature reception signal.
13. The receiver circuit according to claim 8 , wherein said signal-receiving device includes a plurality of reception sensors, each of said plurality of said reception sensors has a directional reception characteristic for sensing radio signals in a predefined spatial segment.
14. A receiver circuit for a communications terminal, comprising:
a signal-receiving device providing K analog reception signals, K being greater than one; and
a signal pre-processing circuit configured downstream from said signal-receiving device, said signal pre-processing circuit including:
an analog/digital converter device having K analog/digital converters connected in parallel for sampling the K reception signals independently of one another with a sufficient sampling rate and for providing K digital signals;
a stage containing K digital zero-inserting elements that are connected in parallel, each of said zero-inserting elements being fed with a respective one of the K digital signals and inserting K−1 zeros per sampling value of the respective one of the K digital signals into the respective one of the K digital signals; and
a digital filter device for filtering the K digital signals with inserted zeros, said digital filter device having K inputs, wherein a k-th input. k=1, . . . K, respectively, is connected to a series of
a number of K−1 leading memory locations; and
a given number of following memory elements each formed by shift registers of a length of K memory locations.