Granted Patent
Utility
US 6,501,817
· Confirmation No. 8311
AREA EFFICIENT REDUNDANCY MULTIPLEXER CIRCUIT TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES PROVIDING SIGNIFICANTLY REDUCED PARASITIC CAPACITANCE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2016-10-19 | OATH |
Oath or Declaration filed | 42 | View | |
| 2001-11-13 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-11-13 | SPEC |
Specification | 16 | View | |
| 2001-11-13 | CLM |
Claims | 6 | View | |
| 2001-11-13 | ABST |
Abstract | 1 | View | |
| 2001-11-13 | DRW |
Drawings-only black and white line drawings | 6 | View | |
| 2001-11-13 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Michael Parris
Colorado Springs, CO
Kim Hardee
Colorado Springs, CO
Attorneys & Agents of Record
Classification
USPC
377/68
H03K17/063
H03K17/693
Prosecution
- Examiner
- RUBIN, MARGARET R
- Art Unit
- 2816
- Customer No.
- 25235
- Docket No.
- UMI-310 CIP
- Confirmation No.
- 8311
Publication
- Pub. No.
- US20020041198A1
- Pub. Date
- 2002-04-11
Patent Term Adjustment
0days
from
SONY CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2016-10-19
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-11-13
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Quick Facts
- Patent No.
- US 6,501,817
- App. No.
- 10/010,336
- Filed
- 2001-11-13
- Granted
- 2002-12-31
- Pub. No.
- US20020041198A1
- Examiner
- RUBIN, MARGARET R
- Art Unit
- 2816
- PTA
- 0 days
External Links