Bit error rate measurement
View Patent ↗A method for testing a digital circuit as a Device under Test—DUT, including determining a Bit Error Rate—BER—value for each one of a determined number of sample points, the BER value representing the ratio of erroneous digital signals to the total number of regarded digital signals, executing a test for each one of the number of sample points by determining whether the determined BER value exceeds a threshold BER value for that sample point, and analyzing the results of executing the test for each one of the number of sample points for providing a statement about the condition of the DUT.
1. A method, comprising:
determining (a) a first bit error rate for a bit signal from a device under test (DUT) when sampling said bit signal at a first sampling point within a bit period, and (b) a second bit error rate for said bit signal when sampling said bit signal at a second sampling point within said bit period; and
concluding that said DUT has failed a test if either (i) said first bit error rate exceeds a bit error rate threshold for said first sampling point, or (ii) said second bit error rate exceeds a bit error rate threshold for said second sampling point.
2. The method of claim 1 , wherein said first sampling point is located along a transition between logical states of said bit signal.
3. The method of claim 1 , further comprising, prior to said determining, analyzing previous measurement data to select a position of said first sampling point.
4. The method of claim 1 , wherein said first sampling point is situated relative to a point that corresponds to a transition between a low bit error rate value and a high bit error rate value for said first bit error rate.
5. The method of claim 1 , further comprising, prior to said determining, selecting said first and second sampling points in order to cover tolerances of the DUT.
6. The method of claim 1 , wherein analyzing the results further comprises:
applying weighing criteria by weighing the determined first bit error rate with a pre-defined weighing factor.
7. The method of claim 1 , wherein said first sample point is located along a transition between (i) a level that represents a first logical state of said bit signal, and (ii) a level that represents a second logical state of said bit signal.
8. The method of claim 1 ,
wherein said first sampling point is defined as being at a first point in time within said bit period, and
wherein said second sampling point is defined as being at a second point in time within said bit period.
9. The method of claim 1 ,
wherein said first sampling point is located in a first half of said bit period to sample said bit signal during transitions between logic levels of said bit signal, and
wherein said second sampling point is located in a second half of said bit period to sample said bit signal during transitions between logic levels of said bit signal.
10. The method of claim 1 ,
wherein said first sampling point is located to sample a positive-going transition of said bit signal, and
wherein said second sampling point is located sample a negative-going transition of said bit signal.
11. The method of claim 1 ,
wherein said determining further comprises:
determining (c) a third bit error rate for said bit signal when sampling said bit signal at a third sampling point within said bit period, and (d) a fourth bit error rate for said bit signal when sampling said bit signal at a fourth sampling point within said bit period,
wherein said concluding concludes said DUT has failed said test if any of (i) said first bit error rate exceeds a bit error rate threshold for said first sampling point, (ii) said second bit error rate exceeds a bit error rate threshold for said second sampling point, (iii) said third bit error rate exceeds a bit error rate threshold for said third sampling point, or (iv) said fourth bit error rate exceeds a bit error rate threshold for said fourth sampling point, and
wherein (A) said first sampling point is located in a first half of said bit period, to sample a positive-going transition of said bit signal, (B) said second sampling point is located in said first half of said bit period, to sample a negative-going transition of said bit signal, (C) said third sampling point is located in a second half of said bit period, to sample a negative-going transition of said bit signal, and (D) said fourth sampling point is located in said second half of said bit period, to sample a positive-going transition of said bit signal.
12. A software program or product, stored on a data carrier, for executing a method when run on a data processing system, said method comprising:
determining (a) a first bit error rate for a bit signal from a device under test (DUT) when sampling said bit signal at a first sampling point within a bit period, and (b) a second bit error rate for said bit signal when sampling said bit signal at a second sampling point within said bit period; and
concluding that said DUT has failed a test if either (i) said first bit error rate exceeds a bit error rate threshold for said first sampling point, or (ii) said second bit error rate exceeds a bit error rate threshold for said second sampling point.
13. The software program or product of claim 12 , wherein said first sample point is located along a transition between (i) a level that represents a first logical state of said bit signal, and (ii) a level that represents a second logical state of said bit signal.
14. A testing unit for testing a digital circuit as a device under test (DUT), comprising:
a processing unit for determining (a) a first bit error rate for a bit signal when sampling said bit signal at a first sampling point within a bit period, and (b) a second bit error rate for said bit signal when sampling said bit signal at a second sampling point within said bit period; and
an analyzing unit for concluding that said DUT has failed a test if either (i) said first bit error rate exceeds a bit error rate threshold for said first sampling point, or (ii) said second bit error rate exceeds a bit error rate threshold for said second sampling point.
15. The testing unit of claim 14 , wherein said first sample point is located along a transition between (i) a level that represents a first logical state of said bit signal, and (ii) a level that represents a second logical state of said bit signal.