Circuitry for determining median of image portions

1. An image sensor on a chip, the image sensor comprising:

a pixel sensor array having column parallel pixel read-out;

a pixel-value analog-data storage buffer coupled with the pixel sensor array to receive analog-data from the column parallel pixel read-out, the pixel-value analog-data storage buffer comprising at least three rows of storage for pixel-value analog data;

median-obtaining circuitry; and

switching circuitry coupled with the pixel-value analog-data storage buffer and with the median-obtaining circuitry to connect different neighborhoods of the pixel-value analog-data storage buffer with the median-obtaining circuitry during at least three processing cycles.

2. The image sensor of claim 1 , wherein the different neighborhoods each comprise a three-by-three pixel-data neighborhood in the pixel-value analog-data storage buffer.

3. The image sensor of claim 1 , further comprising:

an end-of-frame signal line coupled with the column parallel pixel read-out to cause the pixel-value analog-data storage buffer to receive sequential same-row analog data.

4. The image sensor of claim 3 , wherein the pixel-value analog-data storage buffer is wider than the pixel sensor array.

5. The image sensor of claim 1 , wherein the median-obtaining circuitry comprises a plurality of differential pairs.

6. The image sensor of claim 5 , wherein the pixel-value analog-data storage buffer comprises a plurality of capacitors.

7. The image sensor of claim 6 , wherein the switching circuitry connects voltages from the plurality of capacitors to inputs of the plurality of differential pairs.

8. The image sensor of claim 6 , wherein the median-obtaining circuitry further comprises a resistive divider, and wherein the switching circuitry connects voltages from the resistive divider to inputs of the plurality of differential pairs.

9. The image sensor of claim 1 , wherein the median-obtaining circuitry comprises maximum-obtaining circuitry.

10. The image sensor of claim 9 , wherein the maximum-obtaining circuitry comprises source followers tied to a common output line.

11. The image sensor of claim 9 , wherein the maximum-obtaining circuitry comprises winner-take-all circuitry.

12. A method of fabricating an image sensor on a semiconductor chip, the method comprising:

forming a pixel sensor array on the semiconductor chip;

forming a pixel-value analog-data storage buffer comprising at least three rows on the semiconductor chip;

forming median-obtaining circuitry on the semiconductor chip and coupled with the pixel-value analog-data storage buffer, the median-obtaining circuitry including switching circuitry to connect different neighborhoods of the pixel-value analog-data storage buffer with the median-obtaining circuitry during at least three processing cycles; and

coupling the pixel-value analog-data storage buffer with the pixel sensor array on the semiconductor chip such that the pixel-value analog-data storage buffer can receive analog data from the pixel sensor array when in operation.

13. The method of claim 12 , wherein the different neighborhoods each comprise a five-by-five pixel-data neighborhood in the pixel-value analog-data storage buffer.

14. The method of claim 13 , further comprising:

forming an end-of-frame signal line on the semiconductor chip such that the pixel-value analog-data storage buffer can receive sequential same-row analog data from the pixel sensor array when in operation.

15. The method of claim 12 , wherein the pixel sensor array has an actual array size in two dimensions, and wherein the median-obtaining circuitry outputs an effective array size smaller than the actual array size for the pixel sensor array in each of the two dimensions.

16. The method of claim 15 , wherein the median-obtaining circuitry comprises a plurality of differential pairs.

17. The method of claim 16 , wherein the pixel-value analog-data storage buffer comprises a plurality of capacitors.

18. The method of claim 17 , wherein the switching circuitry connects voltages from the plurality of capacitors to inputs of the plurality of differential pairs.

19. The method of claim 15 , wherein the median-obtaining circuitry comprises maximum-obtaining circuitry.

20. The method of claim 19 , wherein the maximum-obtaining circuitry comprises source followers tied to a common output line.

21. The method of claim 19 , wherein the maximum-obtaining circuitry comprises winner-take-all circuitry.