IP Library Granted Patent US 6,941,503
Granted Patent B1
US 6,941,503 · App. 10/016,440 · Granted Sep 6, 2005

Method and apparatus for retaining error-control code protection across block-size discontinuities

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Quick Facts
Patent No.
US 6,941,503
App. No.
10/016,440
Granted
Sep 6, 2005
Kind
B1
Abstract

Each time data, in the form of data blocks protected by code checks, must be reformatted, the original data is broken into new data blocks and a new code check is calculated from, and combined with, each new data block, but the new data blocks and new code checks are both reconstituted versions of the original data blocks and the original code checks. Consequently, the data is never left without protection. In one embodiment, an ingress encoder recomputes an ingress code check from an original data block and its associated header. An egress encoder computes an egress code check from the egress header for an outgoing data block reformatted from the original data block and the ingress code check. The outgoing information is then assembled from the egress header, the outgoing data block and the newly computed egress code check.

Claims (63)

1. A method for retaining error-control code protection across block-size discontinuities occurring between incoming information, having incoming data formatted into ingress data blocks and ingress headers, one ingress header associated with each ingress data block and conveying information about the each ingress data block, and outgoing information having the incoming data reformatted into egress data blocks with sizes different from the ingress data blocks and egress headers, one egress header associated with each egress data block and conveying information about the each egress data block, the method comprising:

(a) generating a code check from data in an ingress data block and from an ingress header associated with the ingress data block;

(b) generating a code check from the code check generated in step (a) and a new egress header associated with an egress data block containing data from the ingress data block but having a different block size; and

(c) generating the outgoing information by combining the new egress header with the associated egress data block and code check generated in step (b).

2. The method of claim 1 wherein step (b) comprises:

(b1) generating a code check from the new egress header;

(b2) generating a code check by subtracting a portion of the code check generated from the associated ingress header in step (a) from the code check generated in step (b1); and

(b3) adding the code check generated in step (a) to the code check generated in step (b2).

3. The method of claim 2 wherein step (b2) comprises adding the inverse of the portion of the code check generated from the ingress header in step (a) to the code check generated in step (b1).

4. The method of claim 1 wherein step (a) further comprises:

(a1) rotating the code check generated from data in the ingress data block and the associated ingress header by an amount equal to the number of non-data bits added to a previous ingress data block.

5. The method of claim 1 wherein step (a) further comprises:

(a2) modifying the incoming information to compensate for non-data bits added to the ingress data block.

6. The method of claim 1 wherein step (c) comprises concatenating the new egress header with the associated egress data block and the code check generated in step (b).

7. The method of claim 1 wherein step (a) comprises generating the code check as a one's-complement sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

8. The method of claim 1 wherein step (b) comprises generating the check code as a one's-complement sum of successive n-bit binary words included in the new egress header.

9. The method of claim 1 wherein step (a) comprises generating the check code as a term-by-term modulo-two sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

10. The method of claim 1 wherein step (b) comprises generating the code check as a term-by-term modulo-two sum of successive n-bit binary words included in the new egress header.

11. The method of claim 1 wherein step (a) comprises generating the code check as the residue of the ingress data block and the associated ingress header modulo a generator polynomial.

12. The method of claim 1 wherein step (b) comprises generating the code check as the residue of the egress data block modulo a generator polynomial.

13. The method of claim 1 wherein the incoming information includes an incoming code check associated with each ingress data block and step (a) further comprises comparing the ingress code check to the incoming code check and generating an error when the ingress code check does not equal the incoming code check.

14. Apparatus for retaining error-control code protection across block-size discontinuities occurring between incoming information, having incoming data formatted into ingress data blocks and ingress headers, one ingress header associated with each ingress data block and conveying information about the each ingress data block, and outgoing information having the incoming data reformatted into egress data blocks with sizes different from the ingress data blocks and egress headers, one egress header associated with each egress data block and conveying information about the each egress data block, the apparatus comprising:

an ingress encoder that generates an ingress code check from data in an ingress data block and from an ingress header associated with the ingress data block;

an egress encoder that generates a egress code check from (1) a new egress header associated with an egress data block containing data from the ingress data block but having a different block size and (2) the ingress code check; and

a multiplexer that generates the outgoing information by combining the new egress header with the associated egress data block and the egress code check.

15. The apparatus of claim 14 wherein the egress encoder comprises:

an outgoing encoder that generates an egress code check from the new egress header and from intermediate contents of the outgoing encoder;

a controller that subtracts a portion of the ingress code check generated from the associated ingress header from the outgoing encoder intermediate contents and adds the ingress code check to the outgoing encoder intermediate contents.

16. The apparatus of claim 15 wherein the controller further comprises a mechanism that modifies the ingress code check to compensate for non-data bits added to the ingress data block.

17. The apparatus of claim 15 wherein the controller comprises a mechanism that rotates the bits of the ingress code check to compensate for non-data bits added to the ingress data block.

18. The apparatus of claim 15 wherein the controller adds the inverse of the portion of the code check generated from the ingress header by the ingress encoder to the outgoing encoder contents.

19. The apparatus of claim 14 further comprising a mechanism that modifies the incoming information to compensate for non-data bits added to the ingress data block.

20. The apparatus of claim 14 wherein the multiplexer comprises a mechanism that concatenates the new egress header with then associated egress data block and the egress code check.

21. The apparatus of claim 14 wherein the ingress encoder comprises a one's-complement encoder that generates a one's-complement sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

22. The apparatus of claim 14 wherein the outgoing encoder comprises a one's-complement encoder that generates a one's-complement sum of successive n-bit binary words included in the new egress header.

23. The apparatus of claim 14 wherein the ingress encoder comprises a vertical-parity-check encoder that generates a term-by-term modulo-two sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

24. The apparatus of claim 14 wherein the outgoing encoder comprises a vertical-parity-check encoder that generates a term-by-term modulo-two sum of successive n-bit binary words included in the new egress header.

25. The apparatus of claim 14 wherein the ingress encoder comprises a cyclic-residue-code encoder that generates the residue of the ingress data block and the associated ingress header modulo a generator polynomial.

26. The apparatus of claim 14 wherein the outgoing encoder comprises a vertical-parity-check encoder that generates the residue of the egress data block modulo a generator polynomial.

27. The apparatus of claim 14 wherein the incoming information includes an incoming code check associated with each ingress data block and the apparatus further comprises a comparator for comparing the ingress code check to the incoming code check and generating an error when the ingress code check does not equal the incoming code check.

28. A computer program product for retaining error-control code protection across block-size discontinuities occurring between incoming information, having incoming data formatted into ingress data blocks and ingress headers, one ingress header associated with each ingress data block and conveying information about the each ingress data block, and outgoing information having the incoming data reformatted into egress data blocks with sizes different from the ingress data blocks and egress headers, one egress header associated with each egress data block and conveying information about the each egress data block, the computer program product comprising a computer usable medium having computer readable program code thereon, including:

program code that generates an ingress code check from data in an ingress data block and from an ingress header associated with the ingress data block;

program code that generates a egress code check from (1) the ingress code check and (2) a new egress header associated with an egress data block containing data from the ingress data block but having a different block size; and

program code that generates the outgoing information by combining the new egress header with the associated egress data block and the egress code check.

29. The computer program product of claim 28 wherein the program code that generates an egress code check comprises:

program code that generates an egress code check from the new egress header;

program code that subtracts a portion of the ingress code check generated from the associated ingress header from the egress code check; and

program code that adds the ingress code check to the egress code check.

30. The computer program product of claim 29 wherein the program code that subtracts a portion of the ingress code check from the egress code check comprises program code that adds the inverse of the portion of the ingress code check to the egress code check generated.

31. The computer program product of claim 28 wherein the program code that generates an ingress code check further comprises program code that rotates the ingress code check by an amount equal to the number of non-data bits added to a previous ingress data block.

32. The computer program product of claim 28 wherein the program code that computes the ingress code check further comprises program code that modifies the incoming information to compensate for non-data bits added to the ingress data block.

33. The computer program product of claim 28 wherein the program code that generates the outgoing information comprises program code that concatenates the new egress header with the associated egress data block and the egress code check.

34. The computer program product of claim 28 wherein the program code that generates the ingress code check comprises program code that generates a one's-complement sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

35. The computer program product of claim 28 wherein the program code that generates the egress code check comprises program code that generates a one's-complement sum of successive n-bit binary words included in the new egress header.

36. The computer program product of claim 28 wherein the program code that generates the ingress code check comprises program code that generates a term-by-term modulo-two sum of successive n-bit binary words included in the ingress data block and the associated ingress header.

37. The computer program product of claim 28 wherein the program code that generates the egress code check comprises program code that generates a term-by-term modulo-two sum of successive n-bit binary words included in the new egress header.

38. The computer program product of claim 28 wherein the program code that generates the ingress code check comprises program code that generates the residue of the ingress data block and the associated ingress header modulo a generator polynomial.

39. The computer program product of claim 28 wherein the program code that generates the egress code check comprises program code that generates the residue of the egress data block modulo a generator polynomial.

40. The computer program product of claim 28 wherein the incoming information includes an incoming code check associated with each ingress data block and wherein the program code that generates the ingress code check further comprises program code that compares the ingress code check to the incoming code check and generates an error when the ingress code check does not equal the incoming code check.

41. A computer data signal embodied in a carrier wave for retaining error-control code protection across block-size discontinuities occurring between incoming information, having incoming data formatted into ingress data blocks and ingress headers, one ingress header associated with each ingress data block and conveying information about the each ingress data block, and outgoing information having the incoming data reformatted into egress data blocks with sizes different from the ingress data blocks and egress headers, one egress header associated with each egress data block and conveying information about the each egress data block, the computer data signal comprising:

program code that generates an ingress code check from data in an ingress data block and from an ingress header associated with the ingress data block;

program code that generates a egress code check from (1) the ingress code check and (2) a new egress header associated with an egress data block containing data from the ingress data block but having a different block size; and

program code that generates the outgoing information by combining the new egress header with the associated egress data block and the egress code check.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL USA L.P.; ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2002
From: CEREVA NETWORKS, INC.
To: EMC CORPORATION
Reel/Frame 013387/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2001
From: HOMBERG, MICHAEL J.; WILS, JORIS; STIFFLER, JACK J.; BOPARDIKAR, RAJU C.
To: CEREVA NETWORKS, INC.
Reel/Frame 012386/0844 →