Picture data memory device with picture data input channels and picture data output channels

1. A picture data memory device,

having a central picture data memory for storing picture data of a plurality of picture data input channels connected to the picture data memory, the picture data memory additionally being connected to a plurality of picture data output channels for reading out and outputting stored picture data for further processing of the output picture data, and

having memory control means for coordinating the individual storage operations of the picture data input channels and the individual read-out operations of the picture data output channels,

wherein each picture data input channel and each picture data output channel are assigned a synchronization signal, the individual synchronization signals being fed to the memory control means, and

wherein the memory control means carry out coordination between the individual storage operations of the picture data input channels and the individual output operations of the picture data output channels taking account of the corresponding synchronization signals.

2. The picture data memory device as claimed in claim 1 , wherein the central picture data memory is an SDRAM memory.

3. The picture data memory device as claimed in claim 1 , wherein the central picture data memory is an eDRAM memory.

4. The picture data memory device as claimed in claim 1 , wherein in the presence of request signals of the individual input and/or output channels for storing and/or for reading out corresponding picture data, the memory control means co-ordinate and process these requests in accordance with a specific priority scheme.

5. The picture data memory device as claimed in claim 4 ,

wherein each input channel comprises an input channel buffer memory which, on the input side, receives and buffer-stores the picture data of the corresponding input channel and, on the output side, is connected to the picture data memory, and

wherein each input channel buffer memory is assigned input channel control means which generate a storage request signal for the memory control means if a specific volume of picture data is stored in the corresponding input channel buffer memory.

6. The picture data memory device as claimed in claim 5 ,

wherein each output channel comprises an output channel buffer memory which, on the input side, is connected to the picture data memory and buffer-stores the picture data of the corresponding output channel which are received from the picture data memory, and

wherein each output channel buffer memory is assigned output channel control means which generate a read-out request signal for the memory control means if the corresponding output channel butler memory has a specific free storage capacity.

7. The picture data memory device as claimed in claim 6 ,

wherein the input channel control means are configured in such a way that, in the presence of a corresponding activation signal from the memory control means, they initiate the storage, in the picture data memory, of a volume of picture data stored in the corresponding input channel buffer memory, and

wherein the output channel control means are configured in such away that, in the presence of a corresponding activation signal from, the memory control means, they initiate the read-out of a specific volume of picture data from the picture data memory and the storage of this volume of picture data in the corresponding output channel buffer memory.

8. The picture data memory device as claimed in claim 7 , wherein the capacity of each input channel buffer memory and of each output channel buffer memory is greater than the volume of picture data transferred per storage or read-out operation.

9. The picture data memory device as claimed in claim 6 , wherein the input channel buffer memory and the output channel buffer memory are in each case formed by a register chain or an SRAM memory.

10. The picture data memory device as claimed in claim 6 , wherein the input channel buffer memory and the output channel buffer memory are connected to the picture data memory via a common bus.

11. The picture data memory device as claimed in claim 4 ,

wherein the memory control means comprise address generator means for generating channel-specific address signals, and

wherein the memory control means, for each request that is currently to be processed in accordance with the specific priority scheme, generates an activation signal for the corresponding input or output channel for carrying out the corresponding storage or read-out operation and instructs the address generator leans for generating a corresponding address signal for the picture data memory.

12. The picture data memory device as claimed in claim 11 ,

wherein the address generator means comprise a dedicated address generator for each input and output channel, and

wherein the synchronization signal of the corresponding input or output channel is applied to each address generator, each address generator being set to a specific start address of the picture data memory synchronously with the synchronization signal applied to said address generator.

13. The picture data memory device as claimed in claim 11 , wherein the generation of the address signals by the address generator means can be manipulated with the aid of corresponding control signals and/or with the aid of corresponding parameterization.

14. The picture data memory device as claimed in claim 1 , wherein each picture data input channel and each picture data output channel are assigned a specific address range in the central picture data memory.

15. The picture data memory device as claimed in claim 1 , wherein at least two of the input channels are asynchronous with respect to one another.

16. The picture data memory device as claimed in claim 1 , wherein at least two of the output channels are asynchronous with respect to one another.

17. The picture data memory device as claimed in claim 1 , wherein at least two input and output channels are asynchronous with respect to one another.