Circuit for generating clock pulses in a communications system
View Patent ↗A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus is provided. In one aspect, a circuit arrangement for a communication system includes a first multiplexer controlled by a first control signal with a plurality of inputs corresponding to a plurality of transmission lines of the interfaces, a respective phase control unit, preceding each input of the first multiplexer, which derives a respective clock generator signal from a received signal of the corresponding transmission line, where the clock generator signal of one of the transmission lines is switched through as output signal of the first multiplexer in dependence on the first control signal, and a phase locked loop, at the inputs of which the output signal of the first multiplexer and a clock from a clock generator operated with an external crystal oscillator.
1. A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus, comprising:
a first multiplexer controlled by a first control signal with a plurality of inputs corresponding to a plurality of transmission lines of the interfaces;
a respective phase control unit, preceding each input of the first multiplexer, which derives a respective clock generator signal from a received signal of a corresponding transmission line;
where the clock generator signal of one of the transmission lines is switched through as output signal of the first multiplexer in dependence on the first control signal;
a phase locked loop, at the inputs of which the output signal of the first multiplexer and a clock from a clock generator operated with an external oscillating crystal, are present and at the output of which an internal reference clock is present which is generated from the output signal of the first multiplexer and the clock from the clock generator;
an output connection for the clock from the clock generator;
a second multiplexer, controlled by a second control signal, at the inputs of which the output signal of the phase locked loop and a reference clock, supplied externally, are present;
where one of the input signals of the second multiplexer is switched through as output signal of the second multiplexer in dependence on the second control signal; and
a clock divider unit, following the second multiplexer for generating the synchronizing clock from the output signal of the second multiplexer.
2. The circuit arrangement as claimed in claim 1 , characterized in that the clock generator signal is generated by a combination of the received signals of at least two transmission lines of the interfaces, particularly by averaging.
3. The circuit arrangement as claimed in claim 1 , characterized in that signals which are transmitted via the transmission lines of the interfaces correspond to an interface protocol of ISDN.
4. The circuit arrangement as claimed in claim 2 , characterized in that signals which are transmitted via the transmission lines of the interfaces correspond to an interface protocol of ISDN.
5. The circuit arrangement as claimed in claim 1 , characterized in that signals which are transmitted via the transmission lines of the interfaces correspond to an XDSL protocol.
6. The circuit arrangement as claimed in claim 2 , characterized in that signals which are transmitted via the transmission lines of the interfaces correspond to an XDSL protocol.
7. The circuit arrangement as claimed in claim 5 , characterized in that the XDSL protocol corresponds to an ADSL or SDSL or VDSL or HDSL protocol.