System and method to screen defect related reliability failures in CMOS SRAMS
View Patent ↗A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.
1. A method of testing a semiconductor wafer, the semiconductor wafer having a plurality of die that contain static random access memory (SRAM) arrays, comprising the steps of:
(a) coupling an array of probes to the semiconductor wafer;
(b) applying a voltage difference across a pair of closely spaced wordlines or bitlines of one or more static random access memory (SRAM) arrays, wherein the voltage difference across the pair of closely spaced wordlines or bitlines exceeds a voltage difference that the wordlines or bitlines would experience in normal operation; and
(c) identifying whether electrical shorting occurs across said pair of closely spaced wordlines or bitlines.
2. The method of claim 1 , further comprising the step of simultaneously applying the voltage difference across respective pairs of substantially all parallel bitline pairs and/or wordline pairs of the one or more SRAM arrays.
3. The method of claim 1 , further comprising the step of simultaneously applying a voltage across respective pairs of substantially all parallel bitline pairs and/or wordlines pairs of the one or more SRAM arrays of more than one die of the semiconductor wafer.
4. The method of claim 1 , further comprising the step of applying the voltage difference across other adjacent, parallel metal lines of the one or more SRAM arrays.
5. The method of claim 1 , further comprising the step of applying the voltage difference at a magnitude of equal to or greater than two times the operational supply voltage.
6. The method of claim 2 , further comprising the step of applying the voltage difference at a magnitude of equal to or greater than two times the operational supply voltage.
7. The method of claim 3 , further comprising the step of applying the voltage difference at a magnitude of equal to or greater than two times the operational supply voltage.
8. The method of claim 4 , further comprising the step of applying the voltage difference at a magnitude of equal to or greater than two times the operational supply voltage.
9. The method of claim 1 , further comprising the step of prerforming step b at an elevated temperature.
10. The method of claim 9 , further comprising the step of applying the voltage difference at a magnitude of equal to or greater than two times the operational supply voltage.
11. The method of claim 3 , further comprising the step of prerforming step b at an elevated temperature.
12. The method of claim 4 , further comprising the step of prerforming step b at an elevated temperature.
13. A semiconductor wafer having one or more die with a static random access memory (SRAM) array integrated therein, comprising:
a test circuit integrated with the SRAM array; and
connections that couple said test circuit to the SRAM array;
wherein during probing, said test circuit applies a voltage difference across a plurality of adjacent bitline pairs and/or worldine pairs of the SRAM array, the voltage difference being larger than an operational supply voltage for the SRAM array, to identify whether electrical shorting occurs across one or more of said plurality of adjacent bitline pairs and/or wordline pairs.