Semiconductor device
View Patent ↗A MOS semiconductor device includes n − -type surface regions, which are extended portions of an n − -type drift layer 12 extended to the surface of the semiconductor chip. Each n − -type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n − -type surface regions 14 and p-type well region 13 including an n + -type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.
1. A semiconductor device comprising:
a semiconductor chip;
a layer with low electrical resistance of a first conductivity type or a second conductivity type in the bottom portion of the semiconductor chip;
a breakdown-voltage sustaining layer above the layer with low electrical resistance, the breakdown-voltage sustaining layer comprising at least one or more semiconductor regions of the first conductivity type;
a well region of the second conductivity type in the surface portion of the breakdown-voltage sustaining layer;
a source region of the first conductivity type in the surface portion of the well region;
surface regions of the first conductivity type, the surface regions being the extended portions of the breakdown-voltage sustaining layer extended to the surface of the semiconductor chip and surrounded by the well region;
a gate electrode above the extended portion of the well region extended between the surface region and the source region with a gate insulation film interposed therebetween;
a source electrode in contact commonly with the source region and the well region;
a drain electrode on the back surface of the layer with low electrical resistance; and
wherein the ratio between the total surface area of the surface regions and the surface area of the well region including the source region being from 0.01 to 0.2.
2. A semiconductor device comprising:
a semiconductor chip;
a layer with low electrical resistance of a first conductivity type or a second conductivity type in the bottom portion of the semiconductor chip; a breakdown-voltage sustaining layer above the layer with low electrical resistance, the breakdown-voltage sustaining layer comprising at least one or more semiconductor regions of the first conductivity type;
a well region of the second conductivity type in the surface portion of the breakdown-voltage sustaining layer;
a source region of the first conductivity type in the surface portion of the well region;
surface regions of the first conductivity type, the surface regions being the extended portions of the breakdown-voltage sustaining layer extended to the surface of the semiconductor chip and surrounded by the well region;
a gate electrode above the extended portion of the well region extended between the surface region and the source region with a gate insulation film interposed therebetween;
a source electrode in contact commonly with the source region and the well region;
a drain electrode on the back surface of the layer with low electrical resistance; and
wherein the shape of the surface regions in the surface of the semiconductor chip is a long stripe.
3. The semiconductor device according to claim 2 , wherein the stripe of the surface region is from 0.1 to 2 μm in width in the main portion thereof.
4. The semiconductor device according to claim 2 , wherein the ratio between the total surface area of the surface regions and the surface area of the well region including the source region is from 0.01 to 0.2.
5. The semiconductor device according to claim 2 , wherein the stripe of the surface region is 100 μm or longer.
6. The semiconductor device according to claim 5 , wherein the stripe of the surface region is 500 μm or longer.
7. A semiconductor device comprising:
a semiconductor chip;
a layer with low electrical resistance of a first conductivity type or a second conductivity type in the bottom portion of the semiconductor chip;
a breakdown-voltage sustaining layer above the layer with low electrical resistance, the breakdown-voltage sustaining layer comprising at least one or more semiconductor regions of the first conductivity type;
a well region of the second conductivity type in the surface portion of the breakdown-voltage sustaining layer;
a source region of the first conductivity type in the surface portion of the well region;
surface regions of the first conductivity type, the surface regions being the extended portions of the breakdown-voltage sustaining layer extended to the surface of the semiconductor chip and surrounded by the well region;
a gate electrode above the extended portion of the well region extended between the surface region and the source region with a gate insulation film interposed therebetween;
a source electrode in contact commonly with the source region and the well region;
a drain electrode on the back surface of the layer with low electrical resistance; and
wherein the gate electrode comprises a plurality of stripes, each surrounded by the well region in a plane parallel to the surface of the semiconductor chip.
8. The semiconductor device according to claim 7 , wherein each of the stripes of the gate electrode covers one or more surface regions.
9. The semiconductor device according to claim 7 , wherein each of the stripes of the gate electrode is from 4 to 8 μm in width in the main portion thereof.
10. The semiconductor device according to claim 9 , wherein each of the stripes of the gate electrode is from 5 to 7 μm in width in the main portion thereof.
11. The semiconductor device according to claim 7 , wherein the stripes of the gate electrode are 100 μm or longer in length.
12. The semiconductor device according to claim 11 , wherein the stripes of the gate electrode are 500 μm or longer in length.