Array substrate for IPS mode liquid crystal display device and method for fabricating the same
View Patent ↗An array substrate of in-plane switching (IPS) mode liquid crystal display device includes auxiliary patterns extended from a first conductive line under the common line in order to prevent a short caused by residues of metallic material that is used for forming a data line and the pixel electrode.
1. An in-plane switching liquid crystal display device comprising:
first and second substrates;
a gate line and a data line defining a pixel region on the first substrate;
a first conductive line formed directly on the first substrate;
a common line on the first conductive line;
a thin film transistor at a crossing portion between the gate and data lines;
a plurality of pixel electrodes on the first substrate;
a plurality of common electrodes on the first substrate;
a first pixel electrode connecting line on the first substrate;
an auxiliary pattern perpendicularly extended from the first conductive line; and
a liquid crystal layer between the first and second substrates.
2. The device of claim 1 , wherein the first pixel electrode connecting line is partially overlapped with the common line.
3. The device of claim 1 , wherein the auxiliary pattern is between the data line and the first pixel electrode connecting line.
4. The device of claim 1 , wherein the auxiliary pattern is formed outermost of the common electrodes.
5. The device of claim 1 , further comprising a second conductive line underneath the gate line.
6. The device of claim 1 , wherein the thin film transistor includes gate, source and drain electrodes.
7. The device of claim 6 , wherein the common electrode is at the same layer as the gate electrode.
8. The device of claim 6 , wherein the pixel electrode is at the same layer as the source and drain electrodes.
9. An in-plane switching liquid crystal display device comprising:
first and second substrates;
a gate line and a data line defining a pixel region on the first substrate;
a first conductive line formed directly on the first substrate;
a common line on the first conductive line;
a thin film transistor at a crossing portion between the gate and data lines;
a plurality of pixel electrodes on the first substrate;
a plurality of common electrodes on the first substrate;
an auxiliary pattern perpendicularly extended from the first conductive line; and
a liquid crystal layer between the first and second substrates.
10. The device of claim 9 , further comprising a first pixel electrode connecting line on the first substrate.
11. The device of claim 10 , wherein the first pixel electrode connecting line is partially overlapped with the common line.
12. The device of claim 10 , wherein the auxiliary pattern is between the data line and the first pixel electrode connecting line.
13. The device of claim 9 , wherein the auxiliary pattern is formed outermost of the common electrodes.
14. The device of claim 9 , further comprising a second conductive line underneath the gate line.
15. The device of claim 9 , wherein the thin film transistor includes gate, source and drain electrodes.
16. The device of claim 15 , wherein the common electrode is at the same layer as the gate electrode.
17. The device of claim 15 , wherein the pixel electrode is at the same layer as the source and drain electrodes.
18. A method for fabricating an in-plane switching liquid crystal display device comprising:
forming a gate line and a data line defining a pixel region on a first substrate;
forming a first conductive line directly on the first substrate;
forming a common line on the first conductive line;
forming a thin film transistor at a crossing portion between the gate and data lines;
forming a plurality of pixel electrodes on the first substrate;
forming a plurality of common electrodes on the first substrate;
forming a first pixel electrode connecting line on the first substrate;
forming an auxiliary pattern perpendicularly extended from the first conductive line; and
forming a liquid crystal layer between the first substrate and a second substrate facing the first substrate.
19. The method of claim 18 , wherein the first pixel electrode connecting line is partially overlapped with the common line.
20. The method of claim 18 , wherein the auxiliary pattern is between the data line and the first pixel electrode connecting line.
21. The method of claim 18 , wherein the auxiliary pattern is formed outermost of the common electrodes.
22. The method of claim 18 , further comprising forming a second conductive line underneath the gate line.
23. The method of claim 18 , wherein the thin film transistor includes gate, source and drain electrodes.
24. The method of claim 23 , wherein the common electrode is formed at the same layer as the gate electrode.
25. The method of claim 23 , wherein the plurality of pixel electrodes are at the same layer as the source and drain electrodes.