IP Library Granted Patent US 7,391,405
Granted Patent B2
US 7,391,405 · App. 10/022,854 · Granted Jun 24, 2008

Method and apparatus for driving liquid crystal display

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Quick Facts
Patent No.
US 7,391,405
App. No.
10/022,854
Granted
Jun 24, 2008
Kind
B2
Abstract

A method and apparatus for driving a liquid crystal display wherein a picture quality can be clearly kept upon conversion of a resolution mode of the liquid crystal display. In the method and apparatus, a reset signal is generated at an enable initiation time of a data enable signal, and a source shift clock for sampling video data is reset in response to the reset signal.

Claims (26)

1. A method of driving a liquid crystal display, comprising the steps of:

receiving a data enable signal from an interface circuit being input to a timing controller for indicating a time interval when a video data exists;

detecting an enable initiation time of the data enable signal;

generating a reset signal at of said enable initiation time of the data enable signal; and

resetting a source shift clock in response to the reset signal, the source shift clock being used for sampling and latching the video data by a source driver that applies the video data into data lines formed on a liquid crystal display panel,

wherein the source shift clock is reset at said enable initiation time in response to the reset signal irrespective of a change in the number of dot clocks upon conversion of a resolution mode.

2. The method according to claim 1 , further comprising the steps of:

sampling and then latching the video data in response to the source shift clock;

applying the latched video data to data lines of the liquid crystal display panel; and

sequentially applying scanning pulses to gate lines of the liquid crystal display panel.

3. A driving apparatus for a liquid crystal display, comprising:

a source shift clock reset unit to detect an enable initiation time of a data enable signal from an interface circuit being input to a timing controller for indicating a time interval when a video data exists to generate a reset signal; and

a reference clock generator to generate a source shift clock for sampling the video data at said enable initiation time, the source shift clock being used for sampling and latching the video data by a source driver that applies the video data into data lines formed on a liquid crystal display panel,

wherein the source shift clock is reset at said enable initiation time in response to the reset signal irrespective of a change in the number of dot clocks upon conversion of a resolution mode.

4. The driving apparatus according to claim 3 , further comprising

a gate driver for sequentially applying scanning pulses to gate lines of the liquid crystal display panel to select scanning lines,

wherein the liquid crystal display panel includes liquid crystal cells provided at pixel areas between the data lines and the gate lines perpendicularly crossing each other and thin film transistors provided at intersections between the data lines and the gate lines to drive the liquid crystal cells, and the timing controller controls the source driver and the gate driver.

5. The driving apparatus according to claim 4 , wherein the source shift clock reset unit and the reference clock generator are included in the timing controller.

6. A driving apparatus for a liquid crystal display, comprising:

a source shift clock reset unit to detect an enable initiation time of a data enable signal for indicating a time interval when a vide data exists to generate a reset signal; and

a reference clock generator to generate a source shift clock for sampling the video data at said enable initiation time, the source shift clock being reset at said enable initiation time in response to the reset signal,

wherein the source shift clock reset unit includes:

a D flip-flop to receive the data enable signal and a dot clock via an input line to delay the data enable signal in accordance with the dot clock;

an inverter to invert the delayed data enable signal;

an AND gate for making a logical product operation of the delayed and inverted enable signal and the data enable signal from the input line to generate a high logic signal for indicating an enable initiation time of the data enable signal; and

a reset part to generate a reset signal for resetting the source shift clock in response to the high logic signal generated in the AND gate.

Assignments (2)
CHANGE OF NAME Recorded Jun 19, 2008
From: LG.PHILIPS LCD CO., LTD.
To: LG DISPLAY CO., LTD.
Reel/Frame 021147/0009 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2002
From: AHN, SEUNG KUK
To: LG.PHILIPS LCD CO., LTD.
Reel/Frame 012704/0277 →