Method and system for predictive multi-component circuit layout generation with reduced design cycle
View Patent ↗One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.
1. A method comprising steps of:
receiving a plurality of parameter values for a multi-component circuit having at least one subcircuit model, said plurality of parameter values comprising at least a slice parameter value, said plurality of parameter values determining a plurality of parasitic values of said multi-component circuit;
generating a layout of said multi-component circuit utilizing said plurality of parameter values, said layout causing said multi-component circuit to have said plurality of parasitic values.
2. The method of claim 1 further comprising a step of utilizing said plurality of parasitic values to simulate an electrical behavior of said multi-component circuit prior to said generating step.
3. The method of claim 1 wherein said plurality of parameter values comprise a style parameter value.
4. The method of claim 3 wherein said style parameter value determines how interconnect lines are routed in said layout of said multi-component circuit.
5. The method of claim 1 wherein said plurality of parameter values comprises a bulk contact parameter value.
6. The method of claim 5 wherein said bulk contact parameter value determines a location for bulk contacts in said layout of said multi-component circuit.
7. The method of claim 1 wherein said plurality of parameter values further comprise finger width, finger length, number of fingers, current, style, and bulk contact parameter values.
8. The method of claim 1 wherein said parasitic values of said at least one subcircuit model comprise a plurality of parasitic resistor values and a plurality of parasitic capacitor values.
9. The method of claim 8 wherein said plurality of parasitic resistor values and said plurality of parasitic capacitor values are determined by said plurality of parameter values.
10. The method of claim 8 further comprising a step of utilizing said plurality of resistor values and said plurality of capacitor values to simulate an electrical behavior of said multi-component circuit prior to said generating step.
11. A method for designing a circuit block including at least one multi-component circuit, said multi-component circuit having at least one subcircuit model, said method comprising steps of:
receiving a plurality of parameter values for said at least one multi-component circuit, said plurality of parameter values comprising at least a slice parameter value;
determining a plurality of parasitic values for said at least one multi-component circuit;
simulating an electrical behavior of said circuit block utilizing said plurality of parasitic values;
generating a layout of said circuit block including said at least one multi-component circuit, said layout causing said at least one multi-component circuit to have said plurality of parasitic values.
12. The method of claim 11 further comprising a step of performing a design rule check after said step of generating said layout.
13. The method of claim 11 further comprising a step of performing a layout versus schematic verification after said step of generating said layout.
14. The method of claim 11 further comprising a step of extracting interconnect parasitics after said step of generating said layout.
15. The method of claim 11 wherein said plurality of parameter values comprise a style parameter value.
16. The method of claim 15 wherein said style parameter value determines how interconnect lines are routed in said layout of said at least one multi-component circuit.
17. The method of claim 11 wherein said plurality of parameter values comprises a bulk contact parameter value.
18. The method of claim 17 wherein said bulk contact parameter value determines a location for bulk contacts in said layout of said at least one multi-component circuit.
19. The method of claim 11 wherein each of said plurality of parameter values further comprise finger width, finger length, number of fingers, current, style, and bulk contact parameter values.
20. The method of claim 11 wherein said parasitic values of said at least one subcircuit model comprise a plurality of parasitic resistor values and a plurality of parasitic capacitor values.
21. The method of claim 20 wherein said plurality of parasitic resistor values and said plurality of parasitic capacitor values are determined by said plurality of parameter values.
22. The method of claim 20 further comprising a step of utilizing said plurality of resistor values and said plurality of capacitor values to simulate an electrical behavior of said at least one multi-component circuit prior to said step of generating said layout.
23. A system comprising a computer for designing a circuit block including at least one multi-component circuit, said at least one multi-component circuit having at least one subcircuit model, said computer implementing a method comprising steps of:
said computer receiving a plurality of parameter values for said at least one multi-component circuit in said circuit block, said plurality of parameter values comprising at least a slice parameter value;
said computer determining a plurality of parasitic values for said at least one multi-component circuit;
said computer generating a layout of said at least one multi-component circuit utilizing said plurality of parameter values, said layout causing said at least one multi-component circuit to have said plurality of parasitic values.
24. The system of claim 23 wherein said method further comprises a step of said computer utilizing said plurality of parasitic values to simulate an electrical behavior of said at least one multi-component circuit prior to said step of said computer generating said layout.
25. The system of claim 23 wherein said method further comprises a step of said computer performing a design rule check after said step of said computer generating said layout.
26. The system of claim 23 wherein said method further comprises a step of said computer performing a layout versus schematic verification after said step of said computer generating said layout.
27. The system of claim 23 wherein said method further comprises a step of said computer extracting interconnect parasitics after said step of said computer generating said layout.
28. The system of claim 23 wherein said plurality of parameter values comprise a style parameter value.
29. The system of claim 28 wherein said style parameter value determines how interconnected lines are routed in said layout of said at least one multi-component circuit.
30. The system of claim 23 wherein said plurality of parameter values comprises a bulk contact parameter value.
31. The system of claim 30 wherein said bulk contact parameter value determines a location for bulk contacts in said layout of said at least one multi-component circuit.
32. The system of claim 23 wherein said plurality of parameter values further comprise finger width, finger length, number of fingers, current, style, and bulk contact parameter values.
33. The system of claim 23 wherein said parasitic values of said at least one subcircuit model comprise a plurality of parasitic resistor values and a plurality of parasitic capacitor values.
34. The system of claim 33 wherein said plurality of parasitic resistor values and said plurality of parasitic capacitor values are determined by said plurality of parameter values.