IP Library Granted Patent US 7,098,983
Granted Patent B2
US 7,098,983 · App. 10/032,057 · Granted Aug 29, 2006

Array substrate for a liquid crystal display device and manufacturing method for the same

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Quick Facts
Patent No.
US 7,098,983
App. No.
10/032,057
Granted
Aug 29, 2006
Kind
B2
Abstract

An array substrate for a liquid crystal display device includes a gate line, a data line including a first data line having a first width and a second data line having a second width overlying the first data line, the second width is larger than the first width, a pixel electrode in a pixel region and defined by a crossing of the gate line and the data line, the pixel electrode being formed during a same process as the second data line, and a thin film transistor connected to the pixel electrode.

Claims (15)

1. An array substrate for a liquid crystal display device, comprising:

a gate line;

a gate insulating layer on the gate line;

a data line on the gate insulating layer, the data line including a first data line having a first width and a second data line having a second width overlying an entire length of the first data line, the second width is larger than the first width;

a passivation layer between the first data line and the second data line;

a pixel electrode in a pixel region, the pixel region being defined by a crossing of the gate line and the data line, the pixel electrode being formed during a same process as the second data line, the pixel electrode being formed of the same material as the second data line; and

a thin film transistor connected to the pixel electrode.

2. The device according to claim 1 , further includes at least one data contact hole in each pixel region for connecting the first data line to the second data line.

3. The device according to claim 1 , wherein the passivation layer is disposed on the thin film transistor.

4. The device according to claim 1 , wherein the first data line includes at least one of molybdenum (Mo), tungsten (W), chromium (Cr), and nickel (Ni).

5. The device according to claim 1 , wherein the second data line and the pixel electrode include at least a transparent conductive material.

6. The device according to claim 5 , wherein the transparent conductive material includes at least indium tin oxide (ITO).

7. The device according to claim 1 , wherein the thin film transistor includes the gate electrode, a first source electrode having a first width connected to the first data line, a second source electrode having a second width connected to the second data line, and a drain electrode spaced apart from the first source electrode.

8. The device according to claim 7 , wherein the second source electrode is formed over the first source electrode.

9. The device according to claim 8 , wherein the second width of the second source electrode is larger than the first width of the first source electrode.