Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications
View Patent ↗A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.
1. A microelectronic device, comprising:
a substrate;
a single semi-insulating silicon carbide layer formed on the substrate, the semi-insulating silicon carbide layer comprising boron and a shallow donor impurity, the semi-insulating silicon carbide layer having boron-related D-center defects formed therein; and
a first semiconductor device formed on the semi-insulating silicon carbide layer, the first semi-conductor device having an active area comprising a high bandgap material.
2. The device of claim 1 , wherein the semi-insulating silicon carbide layer is formed epitaxially.
3. The device of claim 2 , wherein the first semiconductor device is a high frequency, device.
4. The device of claim 2 , wherein the first semiconductor device is a high power device.
5. The device of claim 1 , wherein the substrate is a conductor.
6. The device of claim 1 , wherein the substrate comprises n + silicon carbide.
7. The device of claim 1 , wherein the semi-insulating silicon carbide layer comprises 6H silicon carbide.
8. The device of claim 1 , wherein the semi-insulating silicon carbide layer comprises 4H silicon carbide.
9. The device of claim 1 , wherein the active area of the first semiconductor device comprises silicon carbide.
10. The device of claim 1 , wherein the first semiconductor device comprises a metal-oxide-semiconductor field effect transistor.
11. The device of claim 1 , wherein the first semiconductor device comprises a lateral metal-oxide-semiconductor field effect transistor.
12. The device of claim 1 , wherein the first semiconductor device comprises a bipolar junction transistor.
13. The device of claim 1 , wherein the first semiconductor device comprises a junction field effect transistor.
14. The device of claim 1 , further comprising:
at least a second semiconductor device.
15. The device of claim 14 , wherein the at least a second semiconductor device is found on a portion of the substrate that is physically isolated from the first semiconductor device.
16. The device of claim 14 , wherein the at least a second semiconductor device is found on a portion of the substrate that is electrically isolated from the first semiconductor device.
17. The device of claim 1 , wherein die first semiconductor device is formed epitaxially.
18. An integrated circuit device comprising:
a conducting substrate;
a first single semi-insulating silicon carbide layer formed over a first portion of the conducting substrate, the first single semi-insulating silicon carbide layer comprising boron and a shallow donor impurity, the first single semi-insulating silicon carbide layer having boron-related D-center defects formed therein;
a first device formed over at least part of the first portion of the substrate; and
a second device fanned over a second portion at the substrate different from the first portion,
wherein the first device is electrically isolated from the second device.
19. The integrated circuit device of claim 18 , wherein the first device is formed over at least part of the first semi-insulating silicon carbide layer.
20. The integrated circuit device of claim 18 , wherein the first device is a high power device.
21. The integrated circuit device of claim 20 , wherein the second device is a control device.
22. The integrated circuit device of claim 18 , wherein the first device is a high frequency device.
23. The integrated circuit device of claim 22 , wherein the second device is a control device.
24. The integrated circuit device of claim 19 , wherein the first device is a lateral device.
25. The integrated circuit device of claim 19 , wherein the second device is a control device.
26. The integrated circuit device of claim 19 , wherein the second device is a vertical device.
27. The microelectronic device of claim 1 , wherein the shallow donor impurity is nitrogen.
28. The microelectronic device of claim 1 , wherein the semi-insulating silicon carbide layer is formed by epitaxial growth.
29. The microelectronic device of claim 28 , wherein the shallow donor impurity is nitrogen, and wherein the semi-insulating silicon carbide layer is co-doped with boron and nitrogen during epitaxial growth.
30. The integrated circuit device of claim 18 , wherein the shallow donor impurity is nitrogen.
31. The integrated circuit device of claim 18 , wherein the semi-insulating silicon carbide layer is formed by epitaxial growth.
32. The integrated circuit device of claim 31 , wherein the shallow donor impurity is nitrogen, and wherein the semi-insulating silicon carbide layer is co-doped with boron and nitrogen during epitaxial growth.
33. The integrated circuit device of claim 26 , further comprising a second single semi-insulating silicon carbide layer comprising boron and a shallow donor impurity, the second single semi-insulating silicon carbide layer having boron-related D-center defects formed therein;
wherein the second single semi-insulating silicon carbide layer is formed between the vertical device and the second portion of the conducting substrate, and is electrically isolated from the first semi-insulating silicon carbide layer.
34. The integrated circuit device of claim 18 , further comprising a second single semi-insulating silicon carbide layer comprising boron and a shallow donor impurity, the second single semi-insulating silicon carbide layer having boron-related D-center defects formed therein;
wherein the second single semi-insulating silicon carbide layer is formed between the second device and the second portion of the conducting substrate and is electrically isolated from the first semi-insulating silicon carbide layer.