Fast timing acquisition for multiple radio terminals
View Patent ↗A method and apparatus are provided that performs timing acquisition for multiple radio terminals. According to one aspect of the present invention the invention includes receiving a sequence of symbols modulated onto a carrier frequency over a channel and demodulating the symbols using a clock frequency. The invention further includes determining a frequency offset of the received symbols with respect to the clock frequency and applying the determined frequency offset to adjust the clock frequency.
1. A method comprising:
receiving a sequence of symbols modulated onto a carrier frequency over a channel;
demodulating the symbols using a clock frequency;
determining a frequency offset of the received symbols with respect to the clock frequency;
integrating the frequency offset over a predetermined number of symbols to create an integrator signal; and
applying the integrator signal to adjust the clock frequency.
2. The method of claim 1 wherein the predetermined number of symbols is sufficient to compensate for short term variations in the clock frequency.
3. The method of claim 1 , further comprising analyzing the received symbols for a sequence that identifies a source of the sequence and enabling or disabling the application of the frequency offset to adjust the clock frequency based on the source of the symbols.
4. The method of claim 1 wherein applying the integrator signal comprises applying a voltage to a voltage controlled oscillator.
5. The method of claim 1 wherein determining a frequency offset comprises determining a frequency offset with respect to the carrier frequency.
6. The method of claim 1 wherein the sequence of symbols is modulated onto the carrier frequency using phase shift keying and wherein determining a frequency offset comprises determining a phase rotation of the phase shift keyed symbols.
7. The method of claim 1 further comprising applying the adjusted clock frequency to transmit a sequence of symbols modulated on a carrier frequency.
8. The method of claim 7 wherein the adjusted clock frequency is applied to the transmission rate of the symbol sequence and to the carrier frequency.
9. The method of claim 1 wherein the adjusted clock frequency is a master clock frequency for a terminal.
10. An apparatus comprising:
a receiver to receive a sequence of symbols modulated on a carrier frequency;
an adjustable clock to generate a clock frequency for use in receiving and transmitting;
a demodulator to demodulate the received symbols and to determine a frequency offset of the received symbols with respect to the clock frequency; and
an adjustment drive circuit to receive the frequency offset and generate a clock adjustment signal for application to the adjustable clock, the adjustment drive circuit including a short term integrator to integrate the frequency offset over a predetermined number of symbols.
11. The apparatus of claim 10 wherein the predetermined number of symbols is sufficient to compensate for short term variations in the clock frequency.
12. The apparatus of claim 10 further comprising a deframer to analyze the received symbols for a sequence that identifies a source of the sequence and a switch coupled to the deframer to enable or disable the application of a frequency offset to adjust the clock frequency based on the source of the symbols.
13. The apparatus of claim 10 wherein the adjustable clock comprises a voltage controlled oscillator and wherein the adjustment drive circuit comprises a digital to analog converter to generate an adjustment voltage to apply to the voltage controlled oscillator.
14. The apparatus of claim 10 wherein the frequency offset comprises a frequency offset with respect to the carrier frequency.
15. The apparatus of claim 10 wherein the received symbols are modulated onto the carrier frequency using phase shift keying and wherein the frequency offset comprises a phase rotation of the phase shift keyed symbols.
16. The apparatus of claim 10 further comprising a modulator to modulate a sequence of symbols on a carrier frequency using the adjusted clock frequency.
17. The apparatus of claim 16 wherein the adjusted clock frequency is applied to the transmission rate of the symbol sequence and to the carrier frequency.
18. The apparatus of claim 10 wherein the adjustable clock comprises a master clock for the apparatus.
19. A machine-readable medium having stored thereon data representing instructions which, when executed by a machine, cause the machine to perform operations comprising:
receiving a sequence of symbols modulated onto a carrier frequency over a channel;
demodulating the symbols using a clock frequency;
determining a frequency offset of the received symbols with respect to the clock frequency;
integrating the frequency offset over a predetermined number of symbols to create an integrator signal; and
applying the integrator signal to adjust the clock frequency.
20. The medium of claim 19 wherein the predetermined number of symbols is sufficient to compensate for short term variations in the clock frequency.