Floating point multiplier for delimited operands
View Patent ↗A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
1. A method for providing a floating point product, comprising:
multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages; and
correcting an error introduced by the subprecise operand by:
performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand;
determining the position of a delimiter bit contained within a first significand corresponding to the subprecise operand; and
generating the compensating summand utilizing the determined position of the delimiter bit, wherein the compensating summand is initially equal to a second significand corresponding to the non-subprecise operand.
2. The method of claim 1 , wherein multiplying the subprecise operand and the non-subprecise operand comprises using a multiplier array.
3. The method of claim 1 , wherein generating the compensating summand further comprises:
shifting the compensating summand so that the rightmost bit is aligned with the determined delimiter bit position;
logically inverting the compensating summand; and
adding a logical 1.
4. The method of claim 1 , wherein the subprecise operand is represented using a delimited normalized format with an implicit leading 1-bit.
5. The method of claim 1 , wherein the one of the plurality of intermediate stages is selected wherein a substantial time delay to correct the error is avoided.
6. The method of claim 1 , wherein time consumed by multiplying the subprecise operand and the non-subprecise operand overlaps time consumed in correcting the error.
7. A system for providing a floating point product comprising:
a multiplying circuit for multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages, wherein an error introduced by the subprecise operand is corrected by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand; and
a creating circuit for creating the compensating summand comprising:
a determining circuit for determining the position of a delimiter bit contained within a first significand corresponding to the subprecise operand; and
a generating circuit for generating the compensating summand utilizing the determined position of the delimiter bit, wherein the compensating summand is initially equal to a second significand corresponding to the non-subprecise operand.
8. The system of claim 7 , wherein the multiplying circuit comprises a multiplier array.
9. The system of claim 8 , wherein the multiplier array uses 3-to-2 adders.
10. The system of claim 7 , wherein the generating circuit further comprises:
a shifting circuit for shifting the compensating summand so that the rightmost bit is aligned with the determined delimiter bit position;
a logical inversion circuit for logically inverting the compensating summand; and
a producing circuit for producing a logical 1 to the compensating summand.
11. The system of claim 7 , wherein the subprecise operand is represented using a delimited normalized format with an implicit leading 1-bit.
12. The system of claim 7 , wherein the one of the plurality of intermediate stages is selected wherein a substantial time delay to correct the error is avoided.
13. The system of claim 7 , wherein time consumed by multiplying the subprecise operand and the non-subprecise operand overlaps time consumed in correcting the error.
14. A computer-readable medium on which is stored a set of instructions for providing a floating point product, which when executed perform stages comprising:
multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages; and
correcting an error introduced by the subprecise operand by:
performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand;
determining the position of a delimiter bit contained within a first significand corresponding to the subprecise operand; and
calculating the compensating summand utilizing the determined position of the delimiter bit, wherein the compensating summand is initially equal to a second significand corresponding to the non-subprecise operand.
15. The computer-readable medium of claim 14 , wherein generating the compensating summand further comprises:
shifting the compensating summand so that the rightmost bit is aligned with the determined delimiter bit position;
logically inverting the compensating summand; and
adding a logical 1.
16. The computer-readable medium of claim 14 , wherein the subprecise operand is represented using a delimited normalized format with an implicit leading 1-bit.
17. The computer-readable medium of claim 14 , wherein the one of the plurality of intermediate stages is selected wherein a substantial time delay to correct the error is avoided.
18. The computer-readable medium of claim 14 , wherein time consumed by multiplying the subprecise operand and the non-subprecise operand overlaps time consumed in correcting the error.