IP Library Granted Patent US 6,983,535
Granted Patent B2
US 6,983,535 · App. 10/054,542 · Granted Jan 10, 2006

Insertion of electrical component within a via of a printed circuit board

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Quick Facts
Patent No.
US 6,983,535
App. No.
10/054,542
Granted
Jan 10, 2006
Kind
B2
Abstract

A method for reducing the impedance of a reference path in a printed circuit board includes forming a printed circuit board having a plurality of conductive layers including first, second, third, and fourth layers. The printed circuit board includes two or more vias interconnecting two or more of the conductive layers. A first via is part of a signal path configured to carry a signal from the first layer to the second layer. A second via is part of a reference path configured to carry said signal from a third layer to a fourth conductive layer. The method further includes embedding an electrical component, such as a capacitor, in the second via between two of the conductive layers.

Claims (11)

1. A method for reducing impedance within a reference path in a printed circuit board comprising the steps of:

forming said printed circuit board comprising a plurality of conductive layers, wherein one of said plurality of conductive layers is a first layer, wherein one of said plurality of conductive layers is a second layer, wherein said printed circuit board further comprises two or more vias interconnecting two or more conductive layers of said plurality of conductive layers, wherein a first of said two or more vias is part of a signal path configured to carry said signal from said first layer to said second layer, wherein a second of said two or more vias is part of a reference path configured to carry said signal from a third layer to a fourth conductive layer; and

embedding an electrical component in said second of said two or more vias between two conductive layers of said plurality of conductive layers;

wherein said electrical component has a greater diameter in a center than at ends of said electrical component, wherein each end of said electrical component has a conductive cap which is tinned.

2. The method as recited in claim 1 , wherein said electrical component is a capacitor.

3. The method as recited in claim 1 , wherein said second via of said two or more vias is a via adjacent to said first via of said two or more vias.

4. The method as recited in claim 1 , wherein a diameter from one end of said electrical component changes to an other end of said electrical component, wherein said second via of said two or more vias is configured so that one end of said second via of said two or more vias changes in diameter to an other end of said second via of said two or more vias.

5. The method as recited in claim 4 further comprising the step of:

embedding said electrical component between two conductive layers of said plurality of conductive layers within said printed circuit board by adjusting the diameter of said electrical component and the diameter of said second via of said two or more vias.

6. The method as recited in claim 1 , wherein said electrical component is packaged as a pin, wherein each end of said electrical component is soldered to said two conductive layers of said plurality of conductive layers within said printed circuit board.

7. The method as recited in claim 1 , wherein said second layer is configured to carry said signal to a load, wherein said third layer is configured to return said signal from said load.

Assignments (1)
PATENT ASSIGNMENT AND RESERVATION Recorded Sep 4, 2012
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TOSHIBA GLOBAL COMMERCE SOLUTIONS HOLDINGS CORPORATION
Reel/Frame 028895/0935 →