Granted Patent
Utility
US 6,452,281
· Confirmation No. 3677
SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION PROCESS THEREFOR
Inventor:
Makoto Kanda
|
⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2006-06-20 | EBCC.AD |
Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update | 1 | View | |
| 2002-01-29 | TRNA |
Transmittal of New Application | 1 | View | |
| 2002-01-29 | SPEC |
Specification | 24 | View | |
| 2002-01-29 | CLM |
Claims | 4 | View | |
| 2002-01-29 | ABST |
Abstract | 1 | View | |
| 2002-01-29 | DRW |
Drawings-only black and white line drawings | 6 | View |
Inventors
Makoto Kanda
Fukuyama-shi, JAPAN
Attorneys & Agents of Record
Classification
USPC
257/737
H10P14/47
H10W72/071
H10W72/01255
H10W72/90
H10W72/20
H10W72/29
H10W72/019
Prosecution
- Examiner
- CLARK, SHEILA V
- Art Unit
- 2815
- Customer No.
- 23117
- Docket No.
- 900-415
- Confirmation No.
- 3677
Foreign Priority
2001-019950
·
2001-01-29
·
JAPAN
Publication
- Pub. No.
- US20020100975A1
- Pub. Date
- 2002-08-01
Patent Term Adjustment
-106days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2020-09-11
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Quick Facts
- Patent No.
- US 6,452,281
- App. No.
- 10/058,061
- Filed
- 2002-01-29
- Granted
- 2002-09-17
- Pub. No.
- US20020100975A1
- Examiner
- CLARK, SHEILA V
- Art Unit
- 2815
- PTA
- -106 days
External Links