Low spurious charge pump

1. Phase locked loop charge pump comprising:

a drain node; and

at least a cascode transistor for limiting the variation of the voltage of said drain node,

wherein an intermediate switch transistor is between the drain node and the cascode transistor;

wherein said drain node is a first node and said cascode transistor is a first cascode transistor;

wherein said charge pump further comprises:

a second node, and

a branch connecting the first node with the second node, said branch comprising the first cascode transistor and a second cascode transistor;

wherein a first switch transistor is coupled across from the first cascode transistor, and a second switch transistor is coupled across from the second cascode transistor; and

wherein the intermediate switch transistor is between one of the first node and the second node, and one of the first cascode transistor and the second cascode transistor, and is coupled across from one of the first switch transistor and the second switch transistor.

2. The charge pump of claim 1 , wherein said intermediate switch transistor is a first intermediate switch transistor, and said charge pump further comprises a second intermediate switch transistor, wherein the first intermediate switch transistor is between the first node and the first cascode transistor, said first intermediate switch transistor being coupled across from the first switch transistor, and wherein the second intermediate switch transistor being between the second node and the second cascode transistor, said second intermediate transistor being coupled across from the second switch transistor.

3. The charge pump of claim 2 , wherein the first switch transistor coupled across from the first cascode transistor and/or the second switch transistor coupled across from the second cascode transistor is connected to a further cascode transistor coupled across from at least one of the first and the second cascode transistor.

4. The charge pump of claim 3 , wherein the further cascode transistor is a first additional cascode transistor and wherein the first switch transistor coupled across from the first cascode transistor and the first additional cascode transistor form a dummy branch coupled across from the first cascode transistor and the first intermediate switch transistor, said dummy branch having connections so as to be controlled by the complement signal of the signal controlling at least one of the first intermediate transistor and the second switch transistor coupled across from the second cascode transistor, and wherein a second additional cascode transistor form the dummy branch coupled across from the second cascode transistor and the second intermediate transistor, said dummy branch having connections so as to be controlled by the complement signal of the signal controlling the second intermediate switch transistor.

5. An electronic circuit comprising a charge pump according to claim 1 .

6. An integrated circuit comprising a charge pump according to claim 1 .

7. A phase locked loop charge pump comprising:

a drain node;

a first cascode transistor to limit the variation of the voltage of said drain node;

a first intermediate switch transistor positioned between said drain node and said first cascode transistor; and

a dummy branch with a second cascode transistor connected to a second intermediate switch transistor,

wherein said second intermediate switch transistor is positioned between said drain node and said second cascode transistor.

8. The charge pump of claim 1 , wherein said drain node is a first node and said cascode transistor is a first cascode transistor, said charge pump further comprises:

a second node; a branch connecting the first node with the second node, wherein the branch comprises the first cascode transistor and a second cascode transistor, a first switch transistor across from the first cascode transistor, and a second switch transistor across from the second cascode transistor, and wherein the intermediate switch transistor is between one of the first node and the second node, and one of the first cascode transistor and the second cascode transistor, and the intermediate switch transistor is across from one of the first switch transistor and the second switch transistor.

9. The charge pump of claim 8 , wherein said intermediate switch transistor is a first intermediate switch transistor, and said charge pump further comprises:

a second intermediate switch transistor,

wherein the first intermediate switch transistor is between the first node and the first cascode transistor, and is across from the first switch transistor, and

wherein the second intermediate switch transistor is between the second node and the second cascode transistor and is across from the second switch transistor.

10. The charge pump of claim 9 , wherein at least one of the first switch transistor is across from the first cascode transistor and the second switch transistor is across from the second cascode transistor, and wherein at least one of the first switch transistor and the second switch transistor, is connected to a further cascode transistor across from at least one of the first and the second cascode transistor.

11. The charge pump of claim 10 , wherein the further cascode transistor is a first additional cascode transistor, and wherein the first switch transistor across from the first cascode transistor and the first additional cascode transistor form a dummy branch, the dummy branch is across from the first cascode transistor and the first intermediate transistor, and the dummy branch has connections so as to be controlled by the complement signal of the signal controlling at least one of the first intermediate transistor and the second switch transistor across from the second cascode transistor, and wherein a second additional cascode transistor form the dummy branch, the dummy branch is across from the second cascode transistor and the second intermediate transistor, said dummy branch has connections so as to be controlled by the complement signal of the signal controlling the second intermediate switch transistor.