Method and apparatus for updating an error-correcting code during a partial line store

1. A method for updating an existing error-correcting code for a line when only a portion of the line is updated during a store operation, comprising:

receiving the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line;

reading old data for the portion of the line from the address;

storing the new data to the portion of the line at the address; and

updating the existing error-correcting code for the line to reflect the new data by,

calculating a new error-correcting code for the line from the existing error-correcting code, the old data and the new data, and

replacing the existing error-correcting code with the new error-correcting code:

wherein the acts of reading the old data, storing the new data and updating the existing error-correcting code take place within a single memory operation.

2. The method of claim 1 , wherein the new error-correcting code includes a Hamming code that facilitates single-error correction and double-error detection.

3. The method of claim 1 , wherein calculating the new error-correcting code involves:

calculating a new data error-correcting code for the new data;

calculating an old data error-correcting code for the old data; and

exclusive-ORing the new data error-correcting code, the old data error-correcting code and the existing error-correcting code to produce the new error-correcting code.

4. The method of claim 1 ,

wherein receiving the store operation involves receiving the store operation at an L2 cache from an L1 cache;

wherein reading the old data involves reading the old data from the L2 cache;

wherein storing the new data involves storing the new data to the L2 cache; and

wherein replacing the existing error-correcting code involves replacing the existing error-correcting code in the L2 cache.

5. The method of claim 4 , wherein the L1 cache is a write-through cache, so that all write operations to the L1 cache are propagated to the L2 cache.

6. The method of claim 1 , wherein the single memory operation requires only a single address decode to both read the old data and store the new data.

7. The method of claim 1 , wherein the line is one of:

a cache line; and

a data word.

8. The method of claim 1 , wherein the portion of the line includes one or more bytes within the line.

9. A method for updating an existing error-correcting code for a line when only a portion of the line is updated during a store operation, comprising:

receiving the store operation at an L2 cache from an L1 cache, wherein the store operation includes new data to be stored to the portion of the line;

reading old data for the portion of the line from the L2 cache;

storing the new data to the portion of the line in the L2 cache; and

updating the existing error-correcting code for the line to reflect the new data by,

calculating a new data error-correcting code for the new data,

calculating an old data error-correcting code for the old data, and

exclusive-ORing the new data error-correcting code, the old data error-correcting code and the existing error-correcting code to produce a new error-correcting code for the line, and

replacing the existing error-correcting code with the new error-correcting code in the L2 cache;

wherein the acts of reading the old data, storing the new data and updating the existing error-correcting code take place within a single memory operation.

10. An apparatus that updates an existing error-correcting code for a line when only a portion of the line is updated during a store operation, comprising:

an input that is configured to receive the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line;

a reading mechanism that is configured to read old data for the portion of the line from the address;

a storing mechanism that is configured to store the new data to the portion of the line at the address; and

a calculating mechanism that is configured to calculate a new error-correcting code for the line from the existing error-correcting code, the old data and the new data; and

a replacement mechanism that is configured to replace the existing error-correcting code with the new error-correcting codes;

wherein the apparatus is configured to read the old data, store the new data and update the existing error-correcting code within a single memory operation.

11. The apparatus of claim 10 , wherein the new error-correcting code includes a Hamming code that facilitates single-error correction and double-error detection.

12. The apparatus of claim 10 , wherein the calculating mechanism is configured to:

calculate a new data error-correcting code for the new data;

calculate an old data error-correcting code for the old data; and to

exclusive-OR the new data error-correcting code, the old data error-correcting code and the existing error-correcting code to produce the new error-correcting code.

13. The apparatus of claim 10 , further comprising:

an L1 cache;and

an L2 cache;

wherein the input is configured to receive the store operation at the L2 cache from the L2 cache;

wherein the reading mechanism that is configured to read the old data from the L2 cache;

wherein the storing mechanism is configured store to the new data to the L2 cache; and

wherein the replacement mechanism is configured to replace the existing error-correcting code with the new error-correcting code in the L2 cache.

14. The apparatus of claim 13 , wherein the L1 cache is a write-through cache, so that all write operations to the L1 cache are propagated to the L2 cache.

15. The apparatus of claim 10 , wherein the single memory operation requires only a single address decode to both read the old data and store the new data.

16. The apparatus of claim 10 , wherein the line is one of:

a cache line; and

a data word.

17. The apparatus of claim 10 , wherein the portion of the line includes one or more bytes within the line.

18. A computer system that updates an existing error-correcting code for a line when only a portion of the line is updated during a store operation, comprising:

a processor;

an L1 cache within the processor;

an L2 cache accessed by one or more processors;

an input within the L2 cache that is configured to receive the store operation from the L1 cache, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line;

a reading mechanism that is configured to read old data for the portion of the line from the address in the L2 cache;

a storing mechanism that is configured to store the new data to the portion of the line at the address in the L2 cache; and

a calculating mechanism that is configured to calculate a new error-correcting code for the line from the existing error-correcting code, the old data and the new data; and

a replacement mechanism that is configured to replace the existing error-correcting code with the new error-correcting code in the L2 cache;

wherein the computer system is configured to read the old data, store the new data and update the existing error-correcting code within a single memory operation.

19. The computer system of claim 18 , wherein the new error-correcting code includes a Hamming code that facilitates single-error correction and double-error detection.

20. The computer system of claim 18 , wherein the calculating mechanism is configured to:

calculate a new data error-correcting code for the new data;

calculate an old data error-correcting code for the old data; and to

exclusive-OR the new data error-correcting code, the old data error-correcting code and the existing error-correcting code to produce the new error-correcting code.

21. A method for updating an existing error-detecting code for a line when only a portion of the line is updated during a store operation, comprising:

receiving the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line;

reading old data for the portion of the line from the address;

storing the new data to the portion of the line at the address; and

updating the existing error-detecting code for the line to reflect the new data by,

calculating a new error-detecting code for the line from the existing error-detecting code, the old data and the new data, and

replacing the existing error-detecting code with the new error-detecting code;

wherein the acts of reading the old data, storing the new data and updating the existing error-correcting code take place within a single memory operation.