Customer replacement unit monitor programming cable
View Patent ↗A hardware interface usable to communicate with electrically erasable read-only memory devices and, optionally, other external controls or devices, includes self-monitoring power supply circuitry, an EEPROM driver and noise and signal degradation prevention circuitry, and optional input/output circuitry which provides for programmatically cycling power to the memory device. The self-monitoring power supply circuitry is capable of determining whether a power supply has reached the hardware interface. The EEPROM driver and noise and signal degradation prevention circuitry reduces signal noise and/or signal degradation and driver circuitry for programming, monitoring, and downloading information to and from the EEPROM devices. The digital input/output circuitry is capable of controlling the power supply to the hardware interface, downloading or monitoring information to the hardware interface, or controlling/responding to external devices or controls.
1. A hardware interface usable to program one or more electrically erasable read-only memory devices, comprising: a cable; a terminal connector attached to the cable; a printed wire board assembly located in the terminal connector; digital input/output circuitry provided on the printed wire board assembly; self-monitoring power supply circuitry provided on the printed wire board assembly; and electrical noise and signal degradation reduction circuitry provided on the printed wire board assembly.
2. The hardware interface of claim 1 , wherein the connector is a parallel port connector with one or more parallel control line, and further comprising circuitry provided on the printed wire board assembly to turn on and off a parallel control line to permit programmatic power cycling to a memory device.
3. The hardware interface of claim 2 , wherein turning off of the parallel control line isolates the parallel port from a memory device.
4. The hardware interface of claim 3 , further comprising a plurality of buffers, at least one of which is unused as part of the circuitry on the printed wire board assembly, the memory device having a power supply, wherein the memory device power supply is connected to at least one of the at least one unused buffer.
5. The hardware interface device of claim 1 , wherein the connector and the memory device have a signal data and a signal clock line, and further comprising: a resistor connected in series to the signal data line; a resistor connected in series to the clock line; and a pull-up resistor connected to each of the signal data and signal clock lines, each pull-up resistor being lower in value than the series resistor connected to the signal data and signal clock line respectively.
6. The hardware interface of claim 5 , further including a ribbon cable with ground shields between and around the signal data line and signal clock line.
7. The hardware interface of claim 1 , further comprising; a low-pass frequency RC circuit on the printed wire board assembly to filter noise.
8. The hardware interface of claim 1 , further comprising: a common line connecting the memory device power directly to the power supply and the memory device; and circuitry usable to turn the power supply off or on by means of a digital signal.
9. The hardware interface device of claim 1 , wherein the self-regulating power supply includes a monitor.
10. The hardware interface device of claim 9 , wherein the monitor includes an indicator light.
11. The hardware interface device of claim 10 , wherein the connector includes a window to pass light from the indicator light.
12. The hardware interface device of claim 1 , wherein the memory element is a customer replacement unit monitor.
13. The hardware interface device of claim 1 , wherein the terminal connector is connectable to a central processing unit.
14. The hardware interface device of claim 13 , wherein the central processing unit comprises a programming device.
15. A method for eliminating hot socketing between a computer parallel port and a memory device having a power supply where the parallel port and memory device are connected by a parallel connector, comprising: providing a plurality of buffers, at least one of which is unused, in the parallel connector; connecting the memory device power supply to an unused buffer; and programmatically cycling power to the memory device.
16. A hardware interface usable to program one or more electrically erasable read-only memory devices, comprising: a cable; a terminal connector attached to the cable; a printed wire board assembly located in the terminal connector; and digital circuitry provided on the printed wire board assembly which permits power to the one or more electrically erasable read-only memory devices to be switched on and off via the hardware interface.
17. A method of reducing instances of hot-socketing upon connection or disconnection of the hardware interface of claim 1 , comprising: removing power to the one or more electrically erasable read-only memory devices via the hardware interface during the connection or disconnection of the hardware interface with respect to the one or more electrically erasable read-only memory devices.
18. A method of reducing instances of hot-socketing upon connection or disconnection of the hardware interface of claim 1 , comprising: connecting or disconnecting the hardware interface to the one or more electrically erasable read-only memory devices while power is not applied to the one or more electrically erasable read-only memory devices via the hardware interface.
19. The method of claim 18 , further comprising programmatically controlling power to the one or more memory devices via the hardware interface.