ISDN-based bus interface
View Patent ↗An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.
1. An interface unit disposed between an integrated services digital network (ISDN) based bus and a processor bus, wherein data in the ISDN-based bus is transferred in ISDN frames divided into a plurality of timeslots, the ISDN-based bus comprises an ISDN-oriented modular bus in which data is transferred in common channels which prevents all timeslots of an ISDN frame from being accessed, the interface unit comprising:
a data transfer unit includes
a processor bus interface coupled to a processor bus, the processor bus interface includes
a processor buffer,
an ISDN bus interface coupled to an ISDN-based bus, the ISDN bus interface includes
an ISDN buffer; and
a control unit coupled to the data transfer unit for controlling the transfer of data between the processor bus and ISDN-based bus,
wherein the interface unit facilitates communication between a device coupled to the ISDN-based bus and a device coupled to the processor bus, the interface unit is capable of accessing all timeslots in an ISDN flame for data transfer.
2. The interface unit of claim 1 wherein said processor bus interface is coupled to the ISDN-based bus interface via Sn interface buffer comprising a group of register banks, said group of register banks having a control input terminal.
3. The interface unit of claim 2 wherein the control unit further comprises a register bank control unit coupled to the interface buffer for controlling the group of register banks.
4. The interface unit of claim 1 wherein the ISDN buffer comprises at least one shift register for parallel/serial data conversion.
5. The interface unit of claim 1 wherein The processor bus interconnects a central processing unit, a memory unit and peripheral devices.
6. The interface unit of claim 5 wherein the ISDN-based bus is coupled to voice, data and/or video devices.
7. The interface unit of claim 1 wherein said processor bus is connected to a high-speed data transfer unit.
8. The interface unit of claim 7 wherein the high-speed data transfer unit is a Universal Serial Bus.
9. An interface which to facilitates communication between an ISDN-based bus and a processor bus, the ISDN-based bus transfers data in common channels which prevents all timeslots of an ISDN frame from being accessed, the interface comprising:
a data transfer unit for buffering data that are to be transferred between a device coupled to the processor bus and a device on the ISDN-based bus; and
a control unit coupled to the data transfer unit for controlling the transfer of data between the device coupled to the processor bus and the device coupled to the ISDN-based bus, wherein the interface is capable of accessing all timeslots of an ISDN frame for data transfer.
10. The interface of claim 9 wherein the control unit is programmed to determine the direction of data transfer and which slot or slots to access.
11. The interface of claim 10 either operates in frame-based processing or in slot-based processing.
12. The interface of claim 10 wherein the data transfer unit comprises a memory module for buffering data that are to be transferred between the processor bus and the ISDN-based bus.
13. The interface of claim 12 either operates in frame-based processing or in slot-based processing.
14. The interface of claim 9 wherein the data transfer unit comprises a memory module for buffering data that are to be transferred between the processor bus and the ISDN-based based bus.
15. The interface of claim 14 either operates in frame-based processing or in slot-based processing.
16. The interface of claim 9 either operates in frame-based processing or in slot-based processing.
17. The interface of claim 9 wherein the data transfer unit comprises:
processor bus interface storage (PBIS) block coupled to the processor bus, wherein the PBIS includes a PBIS memory wilt fir buffering data that are to be transferred to or received from the processor bus; and
ISDN-based bus interface storage (IBIS) block coupled to the ISDN-based bus, wherein the IBIS includes an IBIS memory unit for storing data that are to be transferred to or received from the ISDN-based bus.
18. The interface of claim 17 wherein the control unit comprises a control register block (CRB) coupled to the processor bus for receiving control information for programming the interface, wherein based on the information, the appropriate port, time slots and direction are selected for data transfer.
19. The interface of claim 17 wherein the data transfer unit further comprises an interface buffer (IB) coupled to the PBIS and IBIS, the IB provides intermediate buffering of data between the PBIS and IBIS blocks.
20. The interface of claim 19 wherein the IB comprises a plurality of register banks, each register bank comprising a plurality of registers to form a register stack.
21. The interface of claim 19 wherein the IB includes first and second register banks for each data port, wherein each register bank comprises a plurality of registers to form a register stack.
22. The interface of claim 9 wherein the control unit comprises a control register block (CRB) coupled to the processor bus for receiving control information for programming the interface, wherein based on the information, the appropriate port, time slots and direction are selected for data transfer.
23. A method of transferring data between an ISDN-based bus and a processor bus in which the ISDN based bus transfers data in common channels, preventing all timeslots of an ISDN frame from being accessed comprising:
storing data to be transferred between a device coupled tote ISDN-based bus and a device coupled to the processor bus in a data transfer unit of an interface; and
transferring stored data between the device coupled to the ISDN-based bus and the device coupled to the processor bus, wherein all timeslots of an ISDN frame are capable of being accessed for data transfer.
24. An interface disposed between an integrated services digital network (ISDN) based bus and a processor bus, wherein data in the ISDN-based bus is transferred in ISDN frames divided into a plurality of timeslots, the data is transferred in common channels which prevents all timeslots of an ISDN frame from being accessed, the interface comprising:
a data transfer unit includes
a processor bus interface coupled to a processor bus, the processor bus interface includes
a processor buffer,
an ISDN bus interface coupled to an ISDN-based bus, the ISDN bus interface includes an
ISDN buffer; and
a control unit coupled to the data transfer wilt for controlling the transfer of data between the processor bus and ISDN-based bus,
wherein the interface unit facilitates communication between a device coupled to the ISDN-based bus and a device coupled to the processor bus via an universal serial port, the interface unit is capable of accessing all timeslots in an ISDN frame the data transfer.