Reducing effects of noise coupling in integrated circuits with memory arrays
View Patent ↗A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
1. A method of operating a memory array with reduced noise coupling comprising:
providing the memory array having a plurality memory cells interconnected by wordlines, bitlines, and platelines, the memory cells of the array are arranged in a plurality of columns, a column comprises a bitline pair having first and second bitlines coupled to a sense amplifier;
performing a memory access to the array, the access selects one of the columns of memory cells; and
providing a plateline pulse to only the selected column while non-selected columns are not provided with the plateline pluse.
2. The method of claim 1 wherein the memory cells are ferroelectric memory cells.
3. The method of claim 2 wherein the memory cells of the array are arranged in an open bitline, a folded bitline, or a series architecture.
4. The method of claim 1 wherein the memory cells of the array are arranged in an open bitline, a folded bitline, or a series architecture.
5. The method claim 1 wherein non-selected bitlines are set to a defined state.
6. The method of claim 5 wherein the defined state is selected to equal to logic 1, logic 0, reference voltage, or a combination thereof.
7. The method of claim 6 wherein the reference voltage is equal about V DD /2.
8. The method of claim 7 wherein the non-selected bitlines are floated.
9. The method of claim 8 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
10. The method of claim 7 wherein the plateline pulse is equal to logic 1 or logic 0.
11. The method of claim 10 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
12. The method of claim 7 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
13. The method of claim 6 wherein the plateline pulse is equal to logic 1 or logic 0.
14. The method of claim 13 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
15. The method of claim 13 wherein the non-selected bitlines are floated.
16. The method of claim 15 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
17. The method of claim 6 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
18. The method of claim 5 wherein the plateline pulse is equal to logic 1 or logic 0.
19. The method of claim 18 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
20. The method of claim 18 wherein the non-selected bitlines are floated.
21. The method of claim 20 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
22. The method of claim 5 wherein the non-selected bitlines are floated.
23. The method of claim 5 wherein a plateline decoder coupled to the platelines provides the plateline pulse to the selected column.
24. The method of claim 1 wherein:
performing the memory access selects x columns of memory cells, where x is a whole number greater than 1, n adjacent columns of each selected column are non-selected, where n is equal to at least 1; and
providing plateline pulses to the x selected columns.
25. The method of claim 24 wherein 1, some or all x columns are selected for outputting data during the memory access.
26. The method of claim 25 wherein the plateline pulses are equal to logic 1, logic 0, or a combination thereof.
27. The method claim 26 wherein non-selected bitlines are set to a defined state.
28. The method of claim 27 wherein the defined state is selected to equal to logic 1, logic 0, reference voltage, or a combination thereof.
29. The method of claim 28 wherein the non-selected bitlines are floated.
30. The method of claim 27 wherein the non-selected bitlines are floated.
31. The method claim 25 wherein non-selected bitlines are set to a defined state.
32. The method of claim 31 wherein the defined state is selected to equal to logic 1, logic 0, reference voltage, or a combination thereof.
33. The method of claim 32 wherein the non-selected bitlines are floated.
34. The method of claim 31 wherein the non-selected bitlines are floated.
35. The method of claim 24 wherein the plateline pulses are equal to logic 1, logic 0, or a combination thereof.
36. The method claim 35 wherein non-selected bitlines are set to a defined state.
37. The method of claim 36 wherein the defined state is selected to equal to logic 1, logic 0, reference voltage, or a combination thereof.
38. The method of claim 37 wherein the non-selected bitlines are floated.
39. The method of claim 36 wherein the non-selected bitlines are floated.
40. The method claim 24 wherein non-selected bitlines are set to a defined state.
41. The method of claim 40 wherein the defined state is selected to equal to logic 1, logic 0, reference voltage, or a combination thereof.
42. The method of claim 41 wherein the non-selected bitlines are floated.
43. The method of claim 40 wherein the non-selected bitlines are floated.