Method for dicing wafer stacks to provide access to interior structures

1. A method for producing a die assembly comprising:

providing a wafer stack having a first wafer and a second wafer arranged in an overlying relationship with each other, a first portion of the first wafer supporting a first component, a second portion of the first wafer supporting a second component, the first component and the second component being located between the first wafer and the second wafer;

exposing the first portion and the second portion of the first wafer by removing a portion of the second wafer; and

dicing the first wafer between the first component and the second component to form a first die assembly and a second die assembly, the first die assembly including the first portion of the first wafer that extends outwardly beyond the periphery of a first portion of the second wafer, and the second die assembly including the second portion of the first wafer that extends outwardly beyond the periphery of a second portion of the second wafer such that neither the first component nor the second component is located between the first wafer and the second wafer;

wherein the wafer stack includes a third wafer, the second wafer being arranged at least partially between the first wafer and the third wafer; and

wherein exposing a portion of the first wafer comprises:

exposing the first portion and second portion of the first wafer by removing a portion of the third wafer and the portion of the second wafer.

2. The method of claim 1 , wherein the first component is configured to electrically communicate with a component external to the wafer stack.

3. The method of claim 1 , wherein dicing the first wafer between the first component and the second component comprises:

performing a through-cut of the wafer stack to at least partially detach the first die assembly from the wafer stack.

4. The method of claim 1 , wherein exposing the first portion and the second portion of the first wafer comprises:

exposing a portion of the second wafer by removing a portion of the third wafer.

5. The method of claim 1 :

wherein the first component is configured to electrically communicate with a component external to the wafer stack;

wherein the second wafer defines a recessed portion, the recessed portion being arranged in an overlying relationship with the first component, the recessed portion being configured to enable a partial through-cut of the second wafer in a vicinity of the recessed portion such that the first component is not damaged during formation of the partial through-cut; and

wherein exposing the first portion and the second portion of the first wafer compnses:

performing a partial through-cut of the second wafer in the vicinity of the recessed portion such that the first component is not damaged by the partial through-cut.

6. The method of claim 5 , wherein exposing the first portion and second portion of the first wafer comprises:

dicing the second wafer to enable detachment of the portion of the second wafer from the wafer stack; and

removing the portion of the second wafer from the wafer stack.

7. The method of claim 6 , wherein dicing the second wafer comprises:

performing a first partial through-cut and a second partial through-cut of the wafer stack to at least partially detach of a portion of the second wafer from the wafer stack, the portion of the second wafer to be detached being arranged between the first partial through-cut and the second partial through-cut.