Method of fabricating a high-layer-count backplane
View Patent ↗The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.
1. A method of fabricating a multi-layer circuit board, the method comprising:
creating a first layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of a first dielectric material;
creating a second layer arrangement comprising at least four patterned power plane layers, electrically isolated from each other and form the reference plane layers, within the circuit board, each power plane layer having a thickness at least equivalent to the thickness of the three-ounces-per-square-foot-copper, stacked between layers of a second dielectric material having better void-filling capability, during lamination under similar conditions, than the first dielectric material;
creating a third layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of the first dielectric material;
stacking the first, second, and third layer arrangement in that order;
laminating the stacked layer arrangements together such that the first and second layer arrangement interface across a reference plane layer and the second and third layer arrangements interface across a reference plane layer; and
forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, while leaving the power plane layers electrically isolated from each other and from the reference plane layers, within the circuit board.
2. The method of claim 1 , wherein after laminating, the second layer arrangement is substantially at the middle of the multi-layer circuit board.
3. The method of claim 1 , further comprising forming a second plurality of plated thru-holes in the circuit board, the second plurality of plated thru-holes respectively connecting the four plane layers to first power return, first power supply, second power supply, and second power return connector areas on the board surface.
4. The method of claim 1 , wherein the step of creating a second layer arrangement comprises stacking the power plane layers with at least one low-speed trace layer and at least one reference plane layer separating that low-speed trace layer from the power plane layers, that low-speed trace layer and reference plane each stacked between layers of the second dielectric material.
5. A method of fabricating a multi-layer circuit board, the method comprising:
creating a first layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of a first dielectric material;
creating a second layer arrangement comprising at least two patterned power plane layers, each having a thickness at least equivalent to the thickness of three-ounces-per-square-foot copper, stacked between layers of a second dielectric material having better void-filling capability, during lamination under similar conditions, than the first dielectric material;
laminating the first and second layer arrangement together such that the first and second layer arrangement interface across a reference plane layer; and
forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, while leaving the power plane layers electrically isolated from each other and from the reference plane layers, within the circuit board;
wherein the first dielectric material has a lower dielectric loss than the second dielectric material at high-speed frequencies.
6. The method of claim 5 , wherein the first and second dielectric materials each comprise, prior to assembly, sheets of woven glass fiber impregnated with a filler, the second dielectric material having a higher percent-filler content than the first dielectric material.
7. The method of claim 6 , wherein two sheets of the first dielectric material separate each high-speed differential trace layer from each adjacent reference plane layer.
8. A method of fabricating a multi-layer circuit board, the method comprising:
creating a layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of a first dielectric material;
creating a second layer arrangement comprising at least two patterned power plane layers, each having a thickness at least equivalent to the thickness of three-ounces-per-square-foot copper, stacked between layers of a second dielectric material having better void-filling capability, during lamination under similar conditions, than the first dielectric material;
laminating the first and second layer arrangements together such that the first and second layer arrangements interface across a reference plane layer; and
forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, while leaving the power layers electrically isolated from each other and from the reference plane layers, within the circuit board;
wherein the high-speed differential trace layers each comprise a board region within a larger panel region, the panel region comprising a spaced-apart pattern of relatively small flow-impending features near its periphery.
9. The method of claim 8 , wherein the power plane layers comprise approximately the same board and panel regions as the high-speed differential trace layers, the panel region of each power plane layer comprising a substantially solid peripheral plane region having a relatively few patterned channels leading from the board region toward the edges of the panel.
10. A method of fabricating a multi-layer circuit board, the method comprising:
creating a first layer arrangement comprising a plurality of high-speed differential trace layers and a plurality of reference plane layers stacked in an interleaved fashion, each high-speed differential trace layer separated from each adjacent reference plane layer by a layer of a first dielectric material comprising an allylated polyphenylene ether;
creating a second layer arrangement comprising at least two patterned power plane layers, each having a thickness at least equivalent to the thickness of the three-ounces-per-square-foot copper, stacked between layers of a second dielectric material having better void-filling capability, during lamination under similar conditions, than the first electric material, the second dielectric material comprising an FR-4 resin;
laminating the first and second layer arrangement together such that the first and second layer arrangements interface across a reference plane layer; and
forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, while leaving the power plane layers electrically isolated from each other and from the reference plane layers, within the circuit board.