IP Library Granted Patent US 7,016,662
Granted Patent B1
US 7,016,662 · App. 10/070,013 · Granted Mar 21, 2006

Method and apparatus for up-conversion of radio frequency (RF) signals

Assignee: Sirific Wireless Corporation
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Quick Facts
Patent No.
US 7,016,662
App. No.
10/070,013
Granted
Mar 21, 2006
Kind
B1
Abstract

This patent describes a method and system which overcomes the LO-leakage problem of direct conversion and similar RF transmitters. To solve this problem a virtual LO™ signal is generated within the baseband which is tuned to the incoming RF signal. The virtual local oscillator (VLO) signal is constructed using signals that do not contain a significant amount of power (or no power at all) at the wanted output RF frequency. Any errors is generating the virtual LO signal are minimized using a closed loop correction scheme.

Claims (57)

1. A radio frequency (RF) up-convertor with reduced local oscillator leakage, for emulating the modulation of an input signal x(t) with a local oscillator signal having frequency ƒ, said up-convertor comprising:

a synthesizer for generating mixing signals φ 1 and φ 2 which vary irregularly over time, where:

φ 1 *φ 2 has significant power at the frequency ƒ of said local oscillator signal being emulated;

neither φ 1 nor φ 2 has significant power at the frequency ƒ of said local oscillator signal being emulated, and

said mixing signals φ 1 and φ 2 are designed to emulate said local oscillator signal having frequency ƒ in a time domain analysis;

a first mixer coupled to said synthesizer for mixing said input signal x(t) with said mixing signal φ 1 to generate an output signal x(t) φ 1 ; and

a second mixer coupled to said synthesizer and to the output of said first mixer for mixing said signal x(t) φ 1 with said mixing signal φ 2 to generate an output signal x(t) φ 1 φ 2 , said output signal x(t) φ 1 φ 2 emulating the modulation of said input signal x(t) with said local oscillator signal having frequency f.

2. The radio frequency (RF) up-converter of claim 1 wherein said synthesizer further comprises:

a synthesizer for generating mixing signals φ 1 and φ 2 , where φ 1 *φ 1 *φ 2 does not have a significant amount of power within the bandwidth of said output signal x(t) φ 1 φ 2 .

3. The radio frequency (RF) up-convertor of claim 1 wherein said synthesizer further comprises:

a synthesizer for generating mixing signals φ 1 and φ 2 , where φ 1 * φ 2 does not have a significant amount of power within the bandwidth of said output signal x(t) φ 1 φ 2 .

4. The convertor of claim 3 , further comprising:

a closed loop error correction circuit.

5. The radio frequency (RF) up-convertor of claim 4 , wherein said closed loop error correction circuit further comprises:

an error level measurement circuit for measuring an error in said output signal x(t) φ 1 φ 2 ; and

a time-varying signal modification circuit for modifying a parameter of one of said mixing signals φ 1 φ 2 to minimize said error level.

6. The radio frequency (RF) up-convertor of claim 5 , wherein said error level measurement circuit comprises a power measurement.

7. The radio frequency (RF) up-convertor of claim 5 , wherein said error level measurement circuit comprises a voltage measurement.

8. The radio frequency (RF) up-convertor of claim 5 , wherein said error level measurement circuit comprises a current measurement.

9. The radio frequency (RF) up-convertor of claim 5 , wherein said modified parameter is the phase delay of one of said mixing signals φ 1 and φ 2 .

10. The radio frequency (RF) up-convertor of claim 5 , wherein said modified parameter is the fall or rise time of one of said mixing signals φ 1 and φ 2 .

11. The radio frequency (RF) up-convertor of claim 5 , wherein said modified parameter includes both the phase delay and the fall or rise time of one of said mixing signals φ 1 and φ 2 .

12. The radio frequency (RF) up-convertor of claim 4 , wherein said closed loop error correction circuit comprises a digital signal processor (DSP).

13. The radio frequency (RF) up-convertor of claim 4 , wherein said closed loop error correction circuit comprises analogue components.

14. The radio frequency (RF) up-convertor of claim 4 , wherein said closed loop error correction circuit further comprises:

an error level measurement circuit for measuring an error in said output signal x(t) φ 1 ; and

a time-varying signal modification circuit for modifying a parameter of one of said mixing signals φ 1 and φ 2 to minimize said error level.

15. The radio frequency (RF) up-convertor of claim 3 wherein said synthesizer further comprises:

a synthesizer for generating mixing signals φ 1 and φ 2 , where said mixing signals φ 1 and φ 2 can change with time in order to reduce errors.

16. The radio frequency (RF) up-convertor of claim 3 , further comprising:

a DC offset correction circuit.

17. The radio frequency (RF) up-convertor of claim 16 , wherein said DC offset correction circuit comprises:

a DC offset generating circuit for generating a DC offset voltage;

a summer for adding said DC offset voltage to an output of one of said mixers; and

a DC error level measurement circuit for modifying the level of said DC offset voltage to minimize error level.

18. The radio frequency (RF) up-convertor of claim 17 , wherein said DC error level measurement circuit comprises a power measurement circuit.

19. The radio frequency (RF) up-convertor of claim 17 , wherein said DC error level measurement circuit comprises a voltage measurement circuit.

20. The radio frequency (RF) up-convertor of claim 17 , wherein said DC error level measurement circuit comprises a current measurement circuit.

21. The radio frequency (RF) up-convertor of claim 3 , further comprising:

a local oscillator coupled to said synthesizer for providing a periodic signal having a frequency that is an integral multiple of the frequency of said local oscillator signal being emulated.

22. The radio frequency (RF) up-convertor of claim 1 , further comprising: a filter for removing unwanted signal components.

23. The radio frequency (RF) up-convertor of claim 22 , where said filter comprises:

a filter for removing unwanted signal components from said x(t) φ 1 signal.

24. The radio frequency RF up-converter of claim 1 , wherein said mixing signal is a square wave.

25. The radio frequency (RF) up-convertor of claim 1 , wherein said mixing signals φ 1 and φ 2 effect the modulation of an in-phase component of said input signal x(t), and a complementary up-convertor with mixing signals 90 degrees out of phase, is used to effect the modulation of a quadrature component of said input signal x(t).

26. The radio frequency (RF) up-convertor of claim 1 , wherein said synthesizer uses a single time base to generate both mixing signals φ 1 and φ 2 .

27. The radio frequency (RF) up-convertor of claim 1 , wherein said mixing signals φ 1 and φ 2 are digital waveforms.

28. The radio frequency (RF) up-convertor of claim 1 , wherein said mixing signals φ 1 and φ 2 are square waveforms.

29. The radio frequency (RF) up-convertor of claim 1 , where said synthesizer uses different patterns to generate signals φ 1 and φ 2 .

30. An integrated circuit comprising the radio frequency (RF) up-convertor of claim 1 .

31. A method of modulating a baseband signal x(t) comprising the steps of:

generating mixing signals φ 1 and φ 2 which vary irregularly over time, where:

φ 1 *φ 2 has significant power at the frequency ƒ of a local oscillator signal being emulated;

neither φ 1 nor φ 2 has significant power at the frequency ƒ of said local oscillator signal being emulated, and

said mixing signals φ 1 and φ 2 are designed to emulate said local oscillator signal having frequency f, in a time domain analysis;

mixing said input signal x(t) with said mixing signal φ 1 to generate an output signal x(t) φ 1 ; and

mixing said signal x(t) φ 1 with said mixing signal φ 2 to generate an output signal x(t) φ 1 φ 2 .

Assignments (4)
CHANGE OF NAME Recorded Oct 8, 2009
From: SIRIFIC WIRELESS CORPORATION
To: SIRIFIC WIRELESS ULC
Reel/Frame 023337/0817 →
CHANGE OF NAME Recorded Oct 8, 2009
From: SIRIFIC WIRELESS ULC
To: ICERA CANADA ULC
Reel/Frame 023337/0853 →
SECURITY AGREEMENT Recorded Sep 10, 2008
From: SIRIFIC WIRELESS ULC
To: ETV CAPITAL SA
Reel/Frame 021502/0920 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2002
From: MANKU, TAJINDER; SNYDER, CHRIS; WEALE, GARETH
To: SIRIFIC WIRELESS CORPORATION
Reel/Frame 013234/0559 →
Priority Claims (1)
CA 2281236 · Sep 1, 1999 · national