System and method for assured built in self repair of memories
View Patent ↗An embedded memory device having improved BISR capabilities is provided. The embedded memory device includes an internal clock signal for use in accessing a memory array having access to redundant memory cells during normal operation, and a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of the internal clock signal. Further included are a built-in self-test circuit that performs a built-in self-test using the stress clock signal, and a register that stores defective memory addresses detected by the built-in self-test circuit. Redundant control logic is also included that redirects memory access operations to the defective memory addresses to redundant memory cells.
1. A method for performing a high stress built-in self-repair for a memory, comprising the operations of:
providing an internal clock signal for use in accessing a memory array, the memory array having access to redundant memory cells during normal operation;
performing a built-in self-test on the memory array at each power-up event using a stress clock signal, wherein the stress clock signal has a predetermined frequency greater than the internal clock signal, the predetermined frequency simulating functioning of the memory array under stressed environmental and operating conditions, and wherein the stress clock signal is not used during normal memory access operations;
storing defective memory addresses detected by the built-in self-test in a memory block; and
redirecting memory access operations to the defective memory addresses to redundant memory cells.
2. A method as recited in claim 1 , wherein the memory block is a register.
3. A method as recited in claim 1 , wherein the internal clock signal is based on required read and write times for memory cells of the memory array.
4. A method as recited in claim 3 , wherein the internal clock signal is further based on a margin added to the required read and write times for memory cells of the memory array.
5. A method as recited in claim 4 , wherein an amount of optimal margin is derived from expected variations in required read and write times for the memory cells of the memory array due to possible variations in environmental conditions and operating conditions.
6. A method as recited in claim 5 , wherein the internal clock signal is used during normal memory access operations.