IP Library Granted Patent US 6,978,026
Granted Patent B2
US 6,978,026 · App. 10/083,334 · Granted Dec 20, 2005

Circuit arrangement for gaining a stereo subcarrier and an RDS carrier

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,978,026
App. No.
10/083,334
Granted
Dec 20, 2005
Kind
B2
Abstract

According to the invention, a circuit arrangement for gaining a 38 kHz stereo subcarrier and a 57 kHz RDS carrier for decoding a stereo signal comprised in a demodulated FM signal and/or an RDS signal comprised in a demodulated FM signal, having a simple structure with only one PLL and particularly only one voltage-controlled oscillator ( 2 ) is characterized in that the arrangement comprises a phase-locked loop with a loop filter ( 1 ), a voltage-controlled oscillator ( 2 ), a first phase detector ( 3 ) which receives a reference signal having a reference frequency, and a second phase detector ( 4 ), which receives the FM signal, the output signal of the voltage-controlled oscillator ( 2 ) being coupled to both phase detectors ( 3, 4 ) in a form divided down by means of dividers ( 6, 9; 10, 11 ), and the signal fed back to the second phase detector having a frequency of 19 kHz, in that dividers ( 9, 10, 12 ) are provided, by means of which the output signal of the voltage-controlled oscillator ( 2 ) is divided down and which supply the 38 kHz stereo subcarrier and the 57 kHz RDS carrier, in that a frequency control circuit ( 8 ), which is active only upon start-up of the circuit arrangement, compares the two signals applied to the first phase detector ( 3 ) and controls the voltage-controlled oscillator ( 2 ) in a predetermined frequency range around the reference frequency of the reference signal, in that, after reaching the predetermined frequency range, the frequency control circuit ( 8 ) is deactivated and the output signal of the first phase detector ( 3 ) is coupled to the loop filter ( 1 ), and in that subsequently, if the demodulated FM signal should comprise a 19 kHz pilot, the output signal of the second phase detector ( 4 ) is coupled to the loop filter ( 1 ).

Claims (9)

1. A circuit arrangement for gaining a 38 kHz stereo subcarrier and a 57 kHz RDS carrier for decoding a stereo signal comprised in a demodulated FM signal and/or an RDS signal comprised in a demodulated FM signal, characterized in that the arrangement comprises a phase-locked loop with a loop filter ( 1 ), a voltage-controlled oscillator ( 2 ), a first phase detector ( 3 ) which receives a reference signal having a reference frequency, and a second phase detector ( 4 ), which receives the FM signal, the output signal of the voltage-controlled oscillator ( 2 ) being coupled to both phase detectors ( 3 , 4 ) in a form divided down by means of dividers ( 6 , 9 ; 10 , 11 ), and the signal fed back to the second phase detector having a frequency of 19 kHz, in that dividers ( 9 , 10 , 12 ) are provided, by means of which the output signal of the voltage-controlled oscillator ( 2 ) is divided down and which supply the 38 kHz stereo subcarrier and the 57 kHz RDS carrier, in that a frequency control circuit ( 8 ), which is active only upon start-up of the circuit arrangement, compares the reference signal and the output signal of the voltage-controlled oscillator divided down, as applied to the first phase detector ( 3 ), and controls the voltage-controlled oscillator ( 2 ) in a predetermined frequency range around the reference frequency of the reference signal, in that, after reaching the predetermined frequency range, the frequency control circuit ( 8 ) is deactivated and the output signal of the first phase detector ( 3 ) is coupled to the loop filter ( 1 ), and in that subsequently, if the demodulated FM signal should comprise a 19 kHz pilot, the output signal of the second phase detector ( 4 ) is coupled to the loop filter ( 1 ).

2. An arrangement as claimed in claim 1 , characterized in that the input of the loop filter ( 1 ) is coupled again to the output signal of the first phase detector ( 3 ) when the phase-locked loop unlocks during the operation when the output signal of the second phase detector ( 4 ) is coupled to the loop filter ( 1 ).

3. An arrangement as claimed in claim 1 , characterized in that an electronic switch ( 5 ) is provided which is controlled by means of a control logic and by means of which the input of the loop filter ( 1 ) is coupled to a reference potential upon start-up, to the output of the first phase detector ( 3 ) after reaching the predetermined frequency range, and subsequently to the output of the second phase detector ( 4 ) if the demodulated FM signal should comprise a 19 kHz pilot.

4. An arrangement as claimed in claim 1 , characterized in that a pilot detector ( 13 ) is provided which compares both input signals of the second phase detector ( 4 ).

5. An arrangement as claimed in claim 1 , characterized in that at least one of the dividers ( 9 , 10 ) is used in common for gaining the stereo subcarrier, the RDS carrier and/or the input signal of the second phase detector ( 4 ) derived from the output signal of the voltage-controlled oscillator ( 2 ).

6. An arrangement as claimed in claim 1 , characterized in that the voltage-controlled oscillator ( 2 ) has a nominal frequency of 10.944 MHz, and in that the input signal of the first phase detector ( 3 ) derived from the output signal of the voltage-controlled oscillator ( 2 ) is gained by means of a divider ( 6 ) which divides the signal applied thereto by 3485.

7. An arrangement as claimed in claim 1 , characterized in that the reference signal has a reference frequency of 75.368/24 MHz.

8. An arrangement as claimed in claim 1 , characterized in that the first phase detector ( 3 ) is a digital phase detector and the second phase detector ( 4 ) is a linear phase detector.

9. An arrangement as claimed in claim 1 , characterized in that the frequency control circuit ( 8 ) is switched off when, after start-up, the input of the loop filter ( 1 ) is coupled to the output of the first phase detector ( 3 ).

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2018
From: UNILOC LUXEMBOURG S.A.
To: UNILOC 2017 LLC
Reel/Frame 046532/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2018
From: PENDRAGON WIRELESS LLC
To: UNILOC LUXEMBOURG S.A.
Reel/Frame 045338/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: IPG ELECTRONICS 503 LIMITED
To: PENDRAGON WIRELESS LLC
Reel/Frame 028594/0224 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2009
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: IPG ELECTRONICS 503 LIMITED
Reel/Frame 022203/0791 →