Modified glitch latch for use with power saving dynamic register file structures
View Patent ↗In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.
1. A modified glitch latch, said modified glitch latch being a sensing element coupled to a read word line of a retirement payload array, said modified glitch latch comprising:
a modified glitch latch output terminal;
a control circuit, said control circuit comprising a control circuit first input terminal, a control circuit second input terminal and a control circuit output terminal;
a clock signal coupled to said control circuit first input terminal, said clock signal having a first or “A” phase and a second or “B” phase;
a read signal coupled to said control circuit second input terminal, said read signal having a first or inactive phase and a second or active phase, said second or active phase of said read signal corresponding to a shift in position of a read pointer of said retirement payload array, wherein;
a control signal from said control circuit output terminal opens said modified glitch latch only when, both:
said clock signal is in said “B” phase; and
said read signal is in said active phase.
2. The method of claim 1 , wherein;
said retirement payload array comprises M read word lines and N read bit lines, further wherein;
each of said M read word lines is coupled to a corresponding one of M modified glitch latches.
3. The method of claim 2 , wherein;
said number of rows M is equal to 16 and said number of columns N is equal to 192 such that said retirement payload array is a 192 column and 16 row retirement payload array.
4. The method of claim 2 , wherein;
said retirement payload array is a 192 column, 16-read word line register file structure employing a dynamic, full swing pull down read mechanism.
5. A modified glitch latch, said modified glitch latch comprising:
a modified glitch latch first input terminal;
a signal IN coupled to said modified glitch latch first input terminal;
a first inverter, said first inverter comprising a first inverter input terminal coupled to said modified glitch latch first input terminal and a first inverter output terminal;
an OR gate, said OR gate comprising an OR gate first input terminal, an OR gate second input terminal, coupled to said first inverter output terminal, and an OR gate output terminal;
a first NAND gate, said first NAND gate comprising a first NAND gate first input terminal, coupled to said OR gate output terminal, a first NAND gate second input terminal and a first NAND gate output terminal;
a NOR gate, said NOR gate comprising a NOR gate first input terminal, coupled to said NAND gate output terminal, a NOR gate second input terminal, coupled to said modified glitch latch first input terminal and a NOR gate output terminal, coupled to said a first NAND gate second input terminal;
a modified glitch latch output terminal coupled to said NOR gate output terminal;
a control circuit, said control circuit comprising a control circuit first input terminal, a control circuit second input terminal and a control circuit output terminal;
a clock signal coupled to said control circuit first input terminal, said clock signal having a first or “A” phase and a second or “B” phase;
an read signal coupled to said control circuit second input terminal, said read signal having a first or inactive phase and a second or active phase, wherein;
said control circuit output terminal is coupled to said OR gate first input terminal such that a control signal from said control circuit output terminal is coupled to said OR gate first input terminal, further wherein:
said control signal from said control circuit output terminal opens said modified glitch latch only when, both:
said clock signal is in said “B” phase; and
said read signal is in said active phase.
6. The structure of claim 5 , wherein;
said modified glitch latch is a sensing element coupled to a read word line of a retirement payload array and said second or active phase of said read signal corresponds to a shift in position of a read pointer of said retirement payload array.
7. The method of claim 6 , wherein;
said retirement payload array comprises M read word lines and N read bit lines, further wherein;
each of said M read word lines is coupled to a corresponding one of M modified glitch latches.
8. The method of claim 7 , wherein;
said number of rows M is equal to 16 and said number of columns N is equal to 192 such that said retirement payload array is a 192 column and 16 row retirement payload array.
9. The method of claim 7 , wherein;
said retirement payload array is a 192 column, 16-read word line register file structure employing a dynamic, full swing pull down read mechanism.
10. The modified glitch latch of claim 5 , wherein;
said control circuit comprises:
a second inverter, said second inverter comprising a second inverter input terminal, coupled to said control circuit first input terminal, and a second inverter output terminal;
a second NAND gate, said second NAND gate comprising a second NAND gate first input terminal, coupled to said control circuit second input terminal, a second NAND gate second input terminal, coupled to said second inverter output terminal, and a second NAND gate output terminal coupled to said control circuit output terminal.
11. The structure of claim 10 , wherein;
said modified glitch latch is a sensing element coupled to a read word line of a retirement payload array.
12. The method of claim 11 , wherein;
said retirement payload array comprises M read word lines and N read bit lines, further wherein;
each of said M read word lines is coupled to a corresponding one of M modified glitch latches.
13. The method of claim 12 , wherein;
said number of rows M is equal to 16 and said number of columns N is equal to 192 such that said retirement payload array is a 192 column and 16 row retirement payload array.
14. The method of claim 12 , wherein;
said retirement payload array is a 192 column, 16-read word line register file structure employing a dynamic, full swing pull down read mechanism.
15. A method for controlling the operation of a modified glitch latch, said glitch latch being a sensing element coupled to a read word line of a retirement payload array, said method comprising:
receiving a clock signal, said clock signal having a first or “A” phase and a second or “B” phase;
receiving a read signal, said read signal having a first or inactive phase and a second or active phase, said second or active phase of said read signal corresponding to a shift in position of a read pointer of said retirement payload array; and
opening said modified glitch latch only when, both:
said clock signal is in said “B” phase;
and said read signal is in said active phase.
16. The method of claim 15 , wherein;
said retirement payload array comprises M read word lines and N read bit lines, further wherein;
each of said M read word lines is coupled to a corresponding one of M modified glitch latches.
17. The method of claim 16 , wherein;
said number of rows M is equal to 16 and said number of columns N is equal to 192 such that said retirement payload array is a 192 column and 16 row retirement payload array.
18. The method of claim 17 , wherein;
said retirement payload array is a 192 column, 16-read word line register file structure employing a dynamic, full swing pull down read mechanism.