Checkpointing of register file
View Patent ↗The invention performs an extra read from a register of a register file prior to writing to that register. The data from the extra read is stored in a buffer (e.g., another register file). After a “checkpoint” period, a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint. The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint. The register file of the invention may utilize an extra read port with the register file to perform the extra read. The extra read may occur for every write to the register file; alternatively, the extra read may occur for a subset of the writes to the register file.
1. A method for recovering from data errors within a processor, comprising the steps of:
for each cycle of the processor, storing a copy of data from at least one, but not all, registers of a register file within a buffer if new data architected to the registers and if the cycle is not a checkpoint cycle;
checking for data errors within the processor if the cycle is a checkpoint cycle; and
restoring the data from the buffer to the register file in the event of data errors.
2. A method of claim 1 , further comprising loading the new data to the registers after the step of storing.
3. A method of claim 1 , further comprising loading the new data to the registers concurrently with the step of storing.
4. A method of claim 1 , the step of storing the data within the buffer comprising storing the data within a second register file.
5. A method of claim 1 , further comprising the step of flushing the buffer after checking for, and detecting no, data errors.
6. A method of claim 1 , further comprising the step of freezing execution of instructions within pipelines of the processor after detecting data errors.
7. A method of claim 1 , further comprising the step of resetting a program counter of the processor after detecting errors.
8. A method of claim 7 , further comprising a step of re-executing a program through the processor at a time associated with the reset program counter.
9. A method of claim 1 , the step of checking for data errors comprising periodically checking for the data errors at sequential time periods defined by a number of processor clock cycles.
10. A method of claim 1 , further comprising the steps of utilizing an error correction code in connection with data storage to the buffer.
11. A method of claim 1 , the step of checking comprising checking for data errors within the processor each plurality of cycles.
12. A processor with register file data recovery, comprising:
an execution unit having a plurality of pipelines for processing program instructions relative to a program counter;
a register file, wherein one or more stages of the pipelines loads new data to one or more registers of the register file; and
a buffer for storing a copy of data within at least one, but not all, registers prior to loading the new data, and for restoring data to the register file in the event data errors are detected at a checkpoint within the processor;
wherein the buffer is flushed at the checkpoint if no data errors are detected and wherein the checkpoint occurs each plurality of processor cycles.
13. A processor of claim 12 , the buffer comprising a second register file.
14. A processor of claim 12 , the register file comprising an extra read port for reading the data from the register.
15. A processor of claim 12 , the register file comprising a write port for writing the data from the buffer to the register.
16. A processor of claim 12 , further comprising one or more error detectors for detecting the data errors.
17. A processor of claim 16 , the error detectors comprising redundant logic devices.
18. A processor of claim 12 , further comprising error correction code for data recovery of data stored within the buffer.
19. A processor of claim 12 , the buffer reading data within the registers prior to an execution stage for an instruction identifying a write to the registers.
20. A processor of claim 12 , the program counter being reset in connection with the buffer restoring data to the register file.