Area and power efficient VLIW processor with improved speed
View Patent ↗In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.
1. A VLIW processor comprising:
first and second register file banks, said first register file bank comprising a first plurality of read ports and write ports, and said second register file bank comprising a second plurality of read ports and write ports;
first and second data path blocks, said first data path block comprising a first plurality of execution units, and said second data path block comprising a second plurality of execution units;
a first plurality of buses coupling said first plurality of read ports to each of said first and second data path blocks;
a second plurality of buses coupling said second plurality of read ports to each of said first and second data path blocks;
wherein an operand residing in said first plurality of read ports is concurrently accessed by said first data path block and by said second data path block, wherein said operand is used by only one execution unit in said first data path block, and by only one execution unit in said second data path block, during a single clock cycle and wherein a result of an operation performed in said first data path block is written to only said first plurality of write ports without being written to said second plurality of write ports, wherein said VLIW processor does not include a move bus.
2. The VLIW processor of claim 1 wherein an operand residing in said second plurality of read ports is concurrently accessed by said first plurality of execution units in said first data path block and by said second plurality of execution units in said second data path block.
3. The VLIW processor of claim 1 wherein each of said first and second plurality of execution units is selected from the group consisting of an ALU and a multiplier.
4. The VLIW processor of claim 1 wherein a result of an operation performed in said second data path block is accessed only by said second plurality of write ports without being accessed by said first plurality of write ports.
5. A VLIW processor comprising:
a plurality of register file banks, each of said plurality of register file banks comprising a respective plurality of read ports and write ports;
a plurality of data path blocks, each of said plurality of data path blocks comprising a respective plurality of execution units;
a plurality of buses coupling said plurality of register file banks to each of said plurality of data path blocks;
wherein an operand residing in each of said respective plurality of read ports is concurrently accessed by each of said plurality of data path blocks, wherein said operand is used by only one execution unit in each of said plurality of data path blocks, during a single clock cycle and wherein a result of an operation performed in one of said plurality of data path blocks is written to only said respective plurality of write ports, wherein said VLIW processor does not include a move bus.
6. The VLIW processor of claim 5 wherein each of said respective plurality of execution units is selected from the group consisting of an ALU and a multiplier.
7. A VLIW processor comprising:
first and second register file banks, said first register file bank comprising a first plurality of read ports and write ports, and said second register file bank comprising a second plurality of read ports and write ports;
first and second data path blocks, said first data path block comprising a first plurality of execution units, and said second data path block comprising a second plurality of execution units;
a first plurality of buses coupling said first plurality of read ports to each of said first and second data path blocks;
a second plurality of buses coupling said second plurality of read ports to each of said first and second data path blocks;
wherein during a single clock cycle an operand residing in one of said first plurality of read ports is used by only one execution unit in said first plurality of execution units in said first data path block and by only one execution unit in said second plurality of execution units in said second data path block wherein a result of an operation performed in said first data path block is written to only said first plurality of write ports without being written to said second plurality of write ports, wherein said VLIW processor does not include a move bus.
8. The VLIW processor of claim 7 wherein during said single clock cycle an operand residing in one of said second plurality of read ports is used by only one of said first plurality of execution units in said first data path block.
9. The VLIW processor of claim 7 wherein during said single clock cycle an operand residing in one of said second plurality of read ports is used by only one of said second plurality of execution units in said second data path block.
10. The VLIW processor of claim 7 wherein each of said first and second plurality of execution units is selected from the group consisting of an ALU and a multiplier.
11. The VLIW processor of claim 7 wherein a result of an operation performed in said second data path block is accessed only by said second plurality of write ports without being accessed by said first plurality of write ports.