IP Library Granted Patent US 7,031,902
Granted Patent B1
US 7,031,902 · App. 10/087,550 · Granted Apr 18, 2006

Presilicon disk model for design, development and validation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,031,902
App. No.
10/087,550
Granted
Apr 18, 2006
Kind
B1
Abstract

A method for verifying the design of a disk controller circuit to be incorporated into a targeted hard disk drive system having a read/write channel and a head actuator may include steps of emulating reading and writing of data in the read/write channel based upon a model of the read/write channel, emulating a behavior of the head actuator during track seek and track following operations based upon an electromechanical model of the head actuator, providing a disk controller design base for defining integrated circuit elements comprising the disk controller circuit and providing a controller environment to support execution and debug of firmware for operating the disk controller circuit. A plurality of disk functions may be carried out at a time-scaled rate according to a script. The plurality of disk functions includes interaction of at least the read/write model, the electromechanical model, the disk controller design base and the controller environment.

Claims (8)

1. A method for verifying the design of a disk controller circuit to be incorporated into a targeted hard disk drive system, wherein the targeted hard disk drive system comprises a read/write channel and a head actuator, the method comprising the steps of:

emulating reading and writing of data in the read/write channel based upon a model of the read/write channel;

emulating a behavior of the head actuator during track seek and track following operations based upon an electromechanical model of the head actuator;

providing a disk controller design base for defining integrated circuit elements comprising the disk controller circuit;

providing a controller environment to support execution and debug of firmware for operating the disk controller circuit;

performing a plurality of disk functions according to a script, wherein performance of at least one of the plurality of disk functions comprises the execution of the firmware, and wherein the plurality of disk functions comprise interaction of the read/write channel model, the electromechanical model, the disk controller design base and the controller environment.

2. The method of claim 1 , wherein the plurality of disk functions are performed at a time-scaled rate, wherein the time-scaled rate maintains an accurate relative time relationship between the plurality of disk functions performed under direction of the script, and a real-time performance of the disk functions.

3. The method of claim 1 , wherein the plurality of disk functions are performed at a plurality of environmental limits, wherein the models and the design base are made to operate according to their predicted behavior at the environmental limits.

Assignments (5)
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →